EPM5192JC-ES vs EPM5192JC1 Comparison

Detailed side-by-side comparison of EPM5192JC-ES by Intel and EPM5192JC1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC-ES EPM5192JC1
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.45 $48.30
Device Family MAX 5000 β€”
Device Type CPLD (EPLD) β€”
Macrocells 192 β€”
Logic Array Blocks (LABs) 12 β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) β€”
Package 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) [DATA_NEEDED: exact package from datasheet]
Mounting Type Surface Mount [DATA_NEEDED: surface mount or through-hole]
Technology CMOS β€”
Programming Altera MAX+PLUS II or compatible programmer β€”
Operating Temperature [DATA_NEEDED: operating temperature range for ES grade] [DATA_NEEDED: operating temp range]
Supply Voltage [DATA_NEEDED: VCC nominal] β€”
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] unknown
Lead-Free [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Note Datasheet source: Altera MAX 5000 family document, 52 pages β€”
Family β€” MAX 5000 (MAX 5xxx CPLD)
Manufacturer β€” Intel (formerly Altera Corporation)
Macro Cells β€” 192
Usable Gates β€” 3750
Maximum Operating Frequency β€” 62.5 MHz
Supply Voltage (VCC) β€” 5 V (nominal)
Process Technology β€” 0.5 Β΅m CMOS, UV-erasable EPROM
Propagation Delay (typ) β€” [DATA_NEEDED: propagation delay in ns]
I/O Pins β€” [DATA_NEEDED: I/O pin count]
Programming Interface β€” JTAG-compatible (Altera MAX 5xxx)
Logic Blocks (LABs) β€” 24 (8 macrocells per LAB)
AEC-Q100 β€” not_applicable
Lifecycle β€” Obsolete - last-time-buy stock only at franchised distributors

Datasheets & Resources

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