EPM5192JC-ES vs EPM5192JC1 Comparaison
Comparaison détaillée côte à côte de EPM5192JC-ES par Intel et EPM5192JC1 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192JC-ES | EPM5192JC1 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,45 | $48,30 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| Boîtier | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | [DATA_NEEDED: exact package from datasheet] |
| Type de montage | Surface Mount | [DATA_NEEDED: surface mount or through-hole] |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range for ES grade] | [DATA_NEEDED: operating temp range] |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 (MAX 5xxx CPLD) |
| Manufacturer | — | Intel (formerly Altera Corporation) |
| Macro Cells | — | 192 |
| Usable Gates | — | 3750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Process Technology | — | 0.5 µm CMOS, UV-erasable EPROM |
| Propagation Delay (typ) | — | [DATA_NEEDED: propagation delay in ns] |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Programming Interface | — | JTAG-compatible (Altera MAX 5xxx) |
| Logic Blocks (LABs) | — | 24 (8 macrocells per LAB) |
| AEC-Q100 | — | not_applicable |
| Lifecycle | — | Obsolete - last-time-buy stock only at franchised distributors |