EPM5192LC-25 vs EPM5192LC-2N Comparación
Comparación detallada lado a lado de EPM5192LC-25 por Altera y EPM5192LC-2N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC-25 | EPM5192LC-2N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $55,00 | $11,85 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | 192 macrocells (PAL/GAL-style AND-OR array) |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Speed Grade | -25 (25 ns) | -2 (tPD approximately 25 ns) |
| Encapsulado | JLCC-84 (ceramic J-lead chip carrier) | — |
| Tipo de montaje | Surface Mount | Surface Mount (LC package) |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Tensión de alimentación | 5 V (typical, MAX 5000) | 5 V (typical) |
| I/O Standard | TTL-compatible | — |
| Configuration Memory | Non-volatile EPROM (on-chip) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Estado RoHS | Unknown (legacy ceramic package typically non-RoHS) | Compliant (per -N lead-free suffix) |
| Flip-Flops | — | 192 |
| Package Type | — | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Propagation Delay (typical) | — | 25 ns |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |