EPM5192LC-25 vs EPM5192LC-2N 比較
詳細な並列比較: EPM5192LC-25 メーカー: Altera および EPM5192LC-2N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC-25 | EPM5192LC-2N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $55.00 | $11.85 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | 192 macrocells (PAL/GAL-style AND-OR array) |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Speed Grade | -25 (25 ns) | -2 (tPD approximately 25 ns) |
| パッケージ | JLCC-84 (ceramic J-lead chip carrier) | — |
| 実装タイプ | Surface Mount | Surface Mount (LC package) |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |
| 動作温度 | 0C to +70C (commercial) | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| 電源電圧 | 5 V (typical, MAX 5000) | 5 V (typical) |
| I/O Standard | TTL-compatible | — |
| Configuration Memory | Non-volatile EPROM (on-chip) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| RoHS ステータス | Unknown (legacy ceramic package typically non-RoHS) | Compliant (per -N lead-free suffix) |
| Flip-Flops | — | 192 |
| Package Type | — | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Propagation Delay (typical) | — | 25 ns |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |