EPM7128AETC144-10 vs EPM7128AETC144-7N Comparación
Comparación detallada lado a lado de EPM7128AETC144-10 por Altera y EPM7128AETC144-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ ActivoComparación de especificaciones
| Parámetro | EPM7128AETC144-10 | EPM7128AETC144-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,70 | $39,82 |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum User I/Os | 36 | — |
| Pin-to-pin Logic Delay (tPD) | 10 ns | — |
| Maximum Internal Counter Frequency | 98 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Voltage Tolerance | 2.5 V / 3.3 V / 5 V | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Encapsulado | 144-pin TQFP (also referred to as LQFP-144) | 144-pin TQFP |
| Programming Interface | JTAG (IEEE Std. 1149.1) and ByteBlaster | — |
| Non-volatile Memory | EEPROM, instant-on | — |
| Global Clocks / Global OE | 2 / 2 | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | MSL 3 (per JEDEC J-STD-020) | — |
| Estado RoHS | [DATA_NEEDED: rohs status from manufacturer] | Compliant |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 2500 (2.5K gates) |
| Macro Cells | — | 128 |
| User I/Os | — | 36 (in 144-pin TQFP) |
| Maximum Operating Frequency | — | 129.9 MHz |
| Pin-to-Pin Delay | — | 7.5 ns |
| Propagation Delay (tpd) | — | 7.5 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Process Technology | — | CMOS, EEPROM-based |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| Boundary-Scan Test | — | IEEE Std 1149.1 (JTAG) |
| Pin-Compatible With | — | MAX 7000S 5.0V family (144-pin TQFP) |
| Lead-Free | — | Yes |