EPM7128SQC100-15 vs EPM7128SQI100-10 Comparación
Comparación detallada lado a lado de EPM7128SQC100-15 por Altera y EPM7128SQI100-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 ⚠ Última compraAltera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 ObsoleteComparación de especificaciones
| Parámetro | EPM7128SQC100-15 | EPM7128SQI100-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,20 | $9,75 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) | — |
| User I/Os | 84 | 84 |
| Pin-to-Pin Delay (tPD) | 15 ns | 10 ns |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX value] | — |
| Typical Gate Count | 2,500 gates | — |
| Supply Voltage (VCCINT) | 5 V (5% tolerance) | — |
| Programming Technology | EEPROM (in-system programmable via JTAG) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Encapsulado | 100-pin PQFP (Plastic Quad Flat Pack) | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Tipo de montaje | Surface Mount | — |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | Non-compliant (SnPb lead finish - legacy PQFP) | [DATA_NEEDED: RoHS status not in provided data] |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Blocks (LABs) | — | 8 (16 macrocells each) |
| Package Type | — | PQFP-100 |
| Maximum Internal Frequency | — | 125 MHz to 250 MHz |
| Counter Speed | — | Up to 175.4 MHz |
| Operating Voltage (VCC) | — | 5 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| Program/Erase Cycles | — | 100 minimum |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Logic Family | — | CMOS |
| I/O Compatibility | — | TTL-compatible, 5V/3.3V multi-voltage |