EPM7128SQC100-15 vs EPM7128SQI100-10 对比

详细并排对比 EPM7128SQC100-15 出自 Altera 和 EPM7128SQI100-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ 最后一次采购

规格对比

参数 EPM7128SQC100-15 EPM7128SQI100-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $8.20 $9.75
Family MAX 7000 MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macrocells 128 —
Logic Array Blocks (LABs) 4 (16 macrocells each) —
User I/Os 84 84
Pin-to-Pin Delay (tPD) 15 ns 10 ns
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] —
Typical Gate Count 2,500 gates —
Supply Voltage (VCCINT) 5 V (5% tolerance) —
Programming Technology EEPROM (in-system programmable via JTAG) —
JTAG Interface IEEE Std. 1149.1 compliant —
封装 100-pin PQFP (Plastic Quad Flat Pack) —
工作温度 0C to +70C (Commercial) -40C to +85C (Industrial)
安装类型 Surface Mount —
MSL 等级 3 (168 hours) —
RoHS 状态 Non-compliant (SnPb lead finish - legacy PQFP) [DATA_NEEDED: RoHS status not in provided data]
Macro Cells — 128
Usable Gates — 2,500
Logic Blocks (LABs) — 8 (16 macrocells each)
Package Type — PQFP-100
Maximum Internal Frequency — 125 MHz to 250 MHz
Counter Speed — Up to 175.4 MHz
Operating Voltage (VCC) — 5 V
Configuration Memory — EEPROM (non-volatile)
Program/Erase Cycles — 100 minimum
In-System Programming — Yes (JTAG IEEE 1149.1)
Logic Family — CMOS
I/O Compatibility — TTL-compatible, 5V/3.3V multi-voltage

数据手册与资源

浏览全部产品 创建 BOM 获取报价