EPM7256SQC208-10 vs EPM7256SQC208-7N Comparación
Comparación detallada lado a lado de EPM7256SQC208-10 por Intel y EPM7256SQC208-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7256SQC208-10 - MAX 7000S CPLD, 256 Macrocells, 10ns, 208-PQFP | Intel
EPM7256SQC208-10 ObsoleteComparación de especificaciones
| Parámetro | EPM7256SQC208-10 | EPM7256SQC208-7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,20 | $27,20 |
| Series | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 5,000 | 5,000 |
| Number of I/O Pins | 164 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Speed (fCNT) | Up to 175.4 MHz | — |
| Encapsulado | 208-pin PQFP (SQC208) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programmable Technology | EEPROM (in-system programmable) | — |
| JTAG Support (IEEE 1149.1) | Yes | — |
| PCI Compliance | PCI Local Bus Specification 2.2 compliant | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | Commercial (0C to +70C) |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (N suffix = lead-free) |
| Family | — | MAX 7000S |
| User I/O Pins | — | 164 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin) |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | Non-volatile EEPROM (no external config needed) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP capable) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Open-Drain Output | — | Optional per I/O pin |