EPM7256SQC208-10 vs EPM7256SQC208-7N Comparaison
Comparaison détaillée côte à côte de EPM7256SQC208-10 par Intel et EPM7256SQC208-7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM7256SQC208-10 - MAX 7000S CPLD, 256 Macrocells, 10ns, 208-PQFP | Intel
EPM7256SQC208-10 ObsoleteComparaison des spécifications
| Paramètre | EPM7256SQC208-10 | EPM7256SQC208-7N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,20 | $27,20 |
| Series | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 5,000 | 5,000 |
| Number of I/O Pins | 164 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Speed (fCNT) | Up to 175.4 MHz | — |
| Boîtier | 208-pin PQFP (SQC208) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Type de montage | Surface Mount | Surface Mount |
| Programmable Technology | EEPROM (in-system programmable) | — |
| JTAG Support (IEEE 1149.1) | Yes | — |
| PCI Compliance | PCI Local Bus Specification 2.2 compliant | — |
| Température de fonctionnement | 0C to +70C (commercial) | Commercial (0C to +70C) |
| Niveau MSL | 3 (168 hours) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (N suffix = lead-free) |
| Family | — | MAX 7000S |
| User I/O Pins | — | 164 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin) |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | Non-volatile EEPROM (no external config needed) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP capable) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Open-Drain Output | — | Optional per I/O pin |