EPM7256SQC208-10 vs EPM7256SQC208-7N 对比

详细并排对比 EPM7256SQC208-10 出自 Intel 和 EPM7256SQC208-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7256SQC208-10 EPM7256SQC208-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $11.20 $27.20
Series MAX 7000S —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 256 256
Logic Array Blocks (LABs) 16 16
Usable Gates 5,000 5,000
Number of I/O Pins 164 —
Propagation Delay (tPD) 10 ns —
Counter Speed (fCNT) Up to 175.4 MHz —
封装 208-pin PQFP (SQC208) 208-pin PQFP (Plastic Quad Flat Pack)
安装类型 Surface Mount Surface Mount
Programmable Technology EEPROM (in-system programmable) —
JTAG Support (IEEE 1149.1) Yes —
PCI Compliance PCI Local Bus Specification 2.2 compliant —
工作温度 0C to +70C (commercial) Commercial (0C to +70C)
MSL 等级 3 (168 hours) —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] Compliant (N suffix = lead-free)
Family — MAX 7000S
User I/O Pins — 164
Speed Grade — -7 (7.5 ns pin-to-pin)
Maximum Frequency — 128.2 MHz
Supply Voltage (VCC) — 5 V
Technology — CMOS EEPROM
Configuration Memory — Non-volatile EEPROM (no external config needed)
JTAG Interface — IEEE 1149.1 boundary-scan (ISP capable)
Minimum DC Input Voltage — -0.5 V
Input Undershoot Tolerance — -2.0 V for <100 mA, <20 ns
Pin-to-Pin Delay (tPD) — 7.5 ns
Open-Drain Output — Optional per I/O pin

数据手册与资源

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