EPM9320ALC84-15 vs EPM9320LC84-15 Comparación
Comparación detallada lado a lado de EPM9320ALC84-15 por Altera y EPM9320LC84-15 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320ALC84-15 | EPM9320LC84-15 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $17,95 |
| Family | MAX 9000 CPLD | MAX 9000 |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 | 6,000 |
| Propagation Delay (tPD) | 16 ns | 15 ns (max) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5.0 V nominal) |
| User I/O | 56 | — |
| Logic Array Blocks (LABs) | 16 | 20 |
| Technology | CMOS, EEPROM-based configuration | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Encapsulado | 84-pin PLCC (S-PQCC-J84, J-lead) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Tipo de montaje | Through-hole / socket | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: confirm from manufacturer] |
| Nivel de sensibilidad a la humedad (MSL) | MSL-3 (168 hours per fpgalink.com) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead free status] | — |
| RoHS3 Compliance | ROHS3 Compliant (per fpgalink.com listing) | — |
| Series | — | EPM9320 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Frecuencia de reloj máxima | — | 117.6 MHz |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |