EPM9320GC280-15 vs EPM9560GC280-15N Comparación
Comparación detallada lado a lado de EPM9320GC280-15 por Altera y EPM9560GC280-15N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoleteComparación de especificaciones
| Parámetro | EPM9320GC280-15 | EPM9560GC280-15N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,50 | $125,00 |
| Family | MAX 9000 (EPM9320) | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Architecture | CMOS EEPROM-based, Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) 3rd generation |
| Usable Gates | 6,000 | 12,000 (typical) |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 (16 macrocells per LAB) | — |
| Pin-to-Pin Propagation Delay | 15 ns | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Maximum User I/O Pins | 164 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| I/O Voltage Levels | 3.3 V or 5 V (configurable) | — |
| Programmability | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG | — |
| Encapsulado | 280-pin Ceramic Pin Grid Array (CPGA-280) | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Tipo de montaje | Through-hole (PGA socket) | — |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | — |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | ROHS3 compliant (per fpgalink listing) | — |
| Technology Node | CMOS EEPROM, third-generation MAX | — |
| Device Family | — | MAX 9000 |
| Product Type | — | EE PLD / CPLD |
| Macrocell Count | — | 560 |
| Propagation Delay (tPD) | — | 16.6 ns |
| Frecuencia de reloj máxima | — | 117.6 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Maximum Supply Voltage | — | 5.25 V |
| Logic Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| Boundary-Scan (JTAG) | — | IEEE Std. 1149.1 compliant |
| Package Code | — | PGA / CPGA280 |
| Terminal Form | — | PIN/PEG |
| Operating Temperature Grade | — | Commercial |