EPM9320LI84-20 vs EPM9320LC84-15 Comparación
Comparación detallada lado a lado de EPM9320LI84-20 por Altera y EPM9320LC84-15 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320LI84-20 | EPM9320LC84-15 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $12,80 | $17,95 |
| Manufacturer | Altera (acquired by Intel) | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Encapsulado | 84-PLCC (J-Lead, plastic LCC) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Propagation Delay (tPD) | 20 ns | 15 ns (max) |
| Internal Frequency | 118 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Logic Family | CMOS, EEPROM-based | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Tipo de montaje | Surface Mount (PLCC socket-compatible) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm from manufacturer] |
| Process Technology | High-performance CMOS EEPROM | — |
| Series | — | EPM9320 |
| Usable Gates | — | 6,000 |
| Logic Array Blocks (LABs) | — | 20 |
| Frecuencia de reloj máxima | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |