EPM9320LI84-20 vs EPM9320LC84-15 对比

详细并排对比 EPM9320LI84-20 出自 Altera 和 EPM9320LC84-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320LI84-20 EPM9320LC84-15
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $12.80 $17.95
Manufacturer Altera (acquired by Intel) —
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 320 320
User I/Os 60 —
封装 84-PLCC (J-Lead, plastic LCC) 84-pin PLCC (Plastic Leaded Chip Carrier)
Propagation Delay (tPD) 20 ns 15 ns (max)
Internal Frequency 118 MHz —
电源电压 5.0 V —
Logic Family CMOS, EEPROM-based —
Architecture Multiple Array MatriX (MAX) - third generation —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
工作温度 -40 C to +85 C (industrial) -40C to +85C (commercial) [DATA_NEEDED: exact grade]
安装类型 Surface Mount (PLCC socket-compatible) Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: confirm from manufacturer]
Process Technology High-performance CMOS EEPROM —
Series — EPM9320
Usable Gates — 6,000
Logic Array Blocks (LABs) — 20
最大时钟频率 — 117.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5.0 V nominal)
Programmability — 5.0 V in-system programmable (ISP) via JTAG
JTAG Interface — IEEE Std. 1149.1 boundary-scan compliant
Technology — CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX)
Built-in Pull-up Resistors — Yes, on every I/O pin
Architecture Feature — Pin-locking across design iterations

数据手册与资源

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