EPM9320LI84-20 vs EPM9320LC84-15 Comparaison
Comparaison détaillée côte à côte de EPM9320LI84-20 par Altera et EPM9320LC84-15 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9320LI84-20 | EPM9320LC84-15 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,80 | $17,95 |
| Manufacturer | Altera (acquired by Intel) | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Boîtier | 84-PLCC (J-Lead, plastic LCC) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Propagation Delay (tPD) | 20 ns | 15 ns (max) |
| Internal Frequency | 118 MHz | — |
| Tension d'alimentation | 5.0 V | — |
| Logic Family | CMOS, EEPROM-based | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Température de fonctionnement | -40 C to +85 C (industrial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Type de montage | Surface Mount (PLCC socket-compatible) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm from manufacturer] |
| Process Technology | High-performance CMOS EEPROM | — |
| Series | — | EPM9320 |
| Usable Gates | — | 6,000 |
| Logic Array Blocks (LABs) | — | 20 |
| Fréquence d'horloge maximale | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |