EPM9320RC208-15 vs EPM9480RC208-15N Comparación
Comparación detallada lado a lado de EPM9320RC208-15 por Altera y EPM9480RC208-15N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320RC208-15 | EPM9480RC208-15N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $0,00 |
| Device Family | MAX 9000 | — |
| Macro Cells | 320 | 480 |
| Usable Gates | 6,000 | 10,000 |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | — |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | Yes (ISP via JTAG) |
| JTAG Interface | IEEE Std. 1149.1 | IEEE Std. 1149.1 |
| Encapsulado | 208-pin RQFP (Power QFP) | 208-pin RQFP |
| Package Type | 208-BFQFP Exposed Pad | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Estado del ciclo de vida | Obsolete (PDN0706, 2007) | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum Frequency | — | 117.6 MHz |
| Propagation Delay | — | 15 ns (speed grade -15) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Moisture Sensitivity Level | — | MSL 3 (168 Hours) |
| Manufacturer Standard Lead Time | — | 1-7 Days |
| Architecture | — | Multiple Array MatriX (MAX) third-generation |