EPM9320RI208-10N vs EPM9320RI208-20N Comparación
Comparación detallada lado a lado de EPM9320RI208-10N por Altera y EPM9320RI208-20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320RI208-10N | EPM9320RI208-20N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,20 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | — |
| Macro Cells | 320 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum System Clock Frequency | 100 MHz | — |
| Tensión de alimentación | 5 V | — |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | — |
| Encapsulado | 208-pin RQFP (PowerQuad II) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG/ISP) | Yes, 5.0 V ISP via JTAG |
| Rango de temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Estado RoHS | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS status] |
| Lead Finish | Lead-free (matte tin) | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Device Family | — | MAX 9000 (EPM9320) |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 320 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V configurable |
| Package Lead Pitch | — | 0.500 mm |
| Number of Terminals | — | 208 |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Dedicated Input Pins | — | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | — | -0.5 V |
| Minimum DC Input on Dedicated Inputs | — | -0.3 V |
| Input Undershoot/ Overshoot | — | -2.0 V / 7.0 V for <20 ns (no-load) |