EPM9560ARC208-10N vs EPM9560RC208-15 Comparación
Comparación detallada lado a lado de EPM9560ARC208-10N por Altera y EPM9560RC208-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560ARC208-10N | EPM9560RC208-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,20 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay | 10 ns | 15 ns |
| Internal Counter Frequency | 144.9 MHz | — |
| Tensión de alimentación | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Encapsulado | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power Quad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | Yes, via IEEE Std. 1149.1 JTAG |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | -15 (15 ns pin-to-pin) |
| Estado RoHS | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |