EPM9560ARC208-10N vs EPM9560RC208-15 比較
詳細な並列比較: EPM9560ARC208-10N メーカー: Altera および EPM9560RC208-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560ARC208-10N | EPM9560RC208-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.20 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay | 10 ns | 15 ns |
| Internal Counter Frequency | 144.9 MHz | — |
| 電源電圧 | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| パッケージ | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power Quad Flat Pack) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | Yes, via IEEE Std. 1149.1 JTAG |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | -15 (15 ns pin-to-pin) |
| RoHS ステータス | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |