EPM9560ARC208-10N vs EPM9560RC208-15 对比
详细并排对比 EPM9560ARC208-10N 出自 Altera 和 EPM9560RC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9560ARC208-10N | EPM9560RC208-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.20 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay | 10 ns | 15 ns |
| Internal Counter Frequency | 144.9 MHz | — |
| 电源电压 | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| 封装 | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power Quad Flat Pack) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | Yes, via IEEE Std. 1149.1 JTAG |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | -15 (15 ns pin-to-pin) |
| RoHS 状态 | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |