EPM9560ARI240-10 vs EPM9560GC280-15 Comparación
Comparación detallada lado a lado de EPM9560ARI240-10 por Altera y EPM9560GC280-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteComparación de especificaciones
| Parámetro | EPM9560ARI240-10 | EPM9560GC280-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $115,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Usable Gates | 12,000 | — |
| Macro Cells | 560 | 560 |
| User I/O Pins | 191 | — |
| Encapsulado | 240-pin RQFP (PowerQuad Flat Pack) | — |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Internal Frequency | 144.9 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Technology | CMOS, EEPROM-based configuration | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Rango de temperatura de funcionamiento | -40 C to +85 C (industrial) | — |
| Tipo de montaje | Surface Mount | Through-Hole |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Logic Architecture | Multiple Array MatriX (MAX) with global interconnect array | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic CPGA, contains lead) |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 240 | — |
| Terminal Form | Gull Wing | — |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Architecture | — | Multiple Array MatriX (MAX) |
| Estado del ciclo de vida | — | Obsolete (legacy Altera MAX 9000 family) |