EPM9560ARI240-10 vs EPM9560GC280-15 Comparison

Detailed side-by-side comparison of EPM9560ARI240-10 by Altera and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARI240-10 EPM9560GC280-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) EE PLD (CMOS EEPROM-based CPLD)
Usable Gates 12,000 —
Macro Cells 560 560
User I/O Pins 191 —
Package 240-pin RQFP (PowerQuad Flat Pack) —
Pin-to-Pin Propagation Delay 10 ns —
Internal Frequency 144.9 MHz —
Supply Voltage 5.0 V —
Technology CMOS, EEPROM-based configuration CMOS EEPROM, 0.5 um process (MAX third-gen)
Operating Temperature Range -40 C to +85 C (industrial) —
Mounting Type Surface Mount Through-Hole
Configuration Memory EEPROM (non-volatile, instant-on) —
Logic Architecture Multiple Array MatriX (MAX) with global interconnect array —
RoHS Status [DATA_NEEDED: RoHS status] Non-compliant (ceramic CPGA, contains lead)
Moisture Sensitivity Level [DATA_NEEDED: MSL level] —
Number of Terminals 240 —
Terminal Form Gull Wing —
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Programmability — In-System Programmable (ISP) via JTAG IEEE 1149.1
Architecture — Multiple Array MatriX (MAX)
Lifecycle Status — Obsolete (legacy Altera MAX 9000 family)

Datasheets & Resources

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