EPM9560ARI240-10 vs EPM9560GC280-15 Comparaison
Comparaison détaillée côte à côte de EPM9560ARI240-10 par Altera et EPM9560GC280-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteComparaison des spécifications
| Paramètre | EPM9560ARI240-10 | EPM9560GC280-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $115,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Usable Gates | 12,000 | — |
| Macro Cells | 560 | 560 |
| User I/O Pins | 191 | — |
| Boîtier | 240-pin RQFP (PowerQuad Flat Pack) | — |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Internal Frequency | 144.9 MHz | — |
| Tension d'alimentation | 5.0 V | — |
| Technology | CMOS, EEPROM-based configuration | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Plage de température de fonctionnement | -40 C to +85 C (industrial) | — |
| Type de montage | Surface Mount | Through-Hole |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Logic Architecture | Multiple Array MatriX (MAX) with global interconnect array | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic CPGA, contains lead) |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 240 | — |
| Terminal Form | Gull Wing | — |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Architecture | — | Multiple Array MatriX (MAX) |
| Statut du cycle de vie | — | Obsolete (legacy Altera MAX 9000 family) |