EPM9560RC208-15 vs EPM9560ARC208-10 Comparación
Comparación detallada lado a lado de EPM9560RC208-15 por Altera y EPM9560ARC208-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC208-15 | EPM9560ARC208-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 gates |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Encapsulado | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | 35 LABs |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns pin-to-pin) | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Device Family | — | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 macrocells |
| User I/O Pins | — | 153 I/O |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Frequency | — | 144.9 MHz |
| Logic Family | — | CMOS |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP) |
| Recuento de pines | — | 208 pins |