EPM9560RC208-15 vs EPM9560ARC208-10 比較
詳細な並列比較: EPM9560RC208-15 メーカー: Altera および EPM9560ARC208-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560RC208-15 | EPM9560ARC208-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $0.00 |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 gates |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| 電源電圧 | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| パッケージ | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | 35 LABs |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns pin-to-pin) | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Device Family | — | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 macrocells |
| User I/O Pins | — | 153 I/O |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Frequency | — | 144.9 MHz |
| Logic Family | — | CMOS |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP) |
| ピン数 | — | 208 pins |