EPM9560RC208-15 vs EPM9560ARC208-10 对比
详细并排对比 EPM9560RC208-15 出自 Altera 和 EPM9560ARC208-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9560RC208-15 | EPM9560ARC208-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $0.00 |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 gates |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| 电源电压 | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| 封装 | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | 35 LABs |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns pin-to-pin) | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Device Family | — | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 macrocells |
| User I/O Pins | — | 153 I/O |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Frequency | — | 144.9 MHz |
| Logic Family | — | CMOS |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP) |
| 引脚数量 | — | 208 pins |