EPM9560RC208-7 vs EPM9560RC208-15 Comparación
Comparación detallada lado a lado de EPM9560RC208-7 por Altera y EPM9560RC208-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC208-7 | EPM9560RC208-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $18,90 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD / CPLD | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 560 | 12,000 gates |
| Macrocells | 16 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 7 ns (speed grade -7) | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX value] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Supply Voltage (VCCIO) | 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) | — |
| Process Technology | 0.65 um CMOS EEPROM | — |
| Configuration Memory | Non-volatile on-chip EEPROM (no boot PROM required) | — |
| Programming Interface | JTAG (IEEE 1149.1) + Altera ISP | — |
| Encapsulado | 208-pin Power Quad Flat Pack (RQFP-208) | 208-pin RQFP (Power Quad Flat Pack) |
| Temperatura de funcionamiento | 0C to +70C (commercial) / -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Output Drive Current | 160 mA DC sink per pin | — |
| Estado RoHS | Compliant (ROHS3 per distributor listing) | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Tensión de alimentación | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Tipo de montaje | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |