EPM9560RC208-7 vs EPM9560RC208-15 Comparaison
Comparaison détaillée côte à côte de EPM9560RC208-7 par Altera et EPM9560RC208-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560RC208-7 | EPM9560RC208-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,90 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD / CPLD | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 560 | 12,000 gates |
| Macrocells | 16 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 7 ns (speed grade -7) | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX value] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Supply Voltage (VCCIO) | 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) | — |
| Process Technology | 0.65 um CMOS EEPROM | — |
| Configuration Memory | Non-volatile on-chip EEPROM (no boot PROM required) | — |
| Programming Interface | JTAG (IEEE 1149.1) + Altera ISP | — |
| Boîtier | 208-pin Power Quad Flat Pack (RQFP-208) | 208-pin RQFP (Power Quad Flat Pack) |
| Température de fonctionnement | 0C to +70C (commercial) / -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Output Drive Current | 160 mA DC sink per pin | — |
| Statut RoHS | Compliant (ROHS3 per distributor listing) | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Tension d'alimentation | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Type de montage | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |