EPM9560RC240-10N vs EPM9560ARI240-10N Comparación
Comparación detallada lado a lado de EPM9560RC240-10N por Intel y EPM9560ARI240-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N ⚠ Última compraIntel
EPM9560ARI240-10N - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
EPM9560ARI240-10N NrndComparación de especificaciones
| Parámetro | EPM9560RC240-10N | EPM9560ARI240-10N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $168,00 | $105,00 |
| Family | MAX 9000 | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | Multiple Array MatriX (MAX) - 3rd generation |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/Os | 212 | 216 (per digchip); 191 (per Mouser) |
| Internal Operating Frequency | 144.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| Tensión de alimentación | 5.0 V | 5.0 V nominal (4.5 V min, 5.5 V max) |
| Process Technology | 0.65 µm CMOS EEPROM | — |
| Encapsulado | 240-pin RQFP (Plastic Quad Flat Pack) | 240-pin RQFP (RQFP-240 / PQFP-240) |
| Programming Interface | JTAG (IEEE 1149.1) - in-system programmable | — |
| I/O Standards Supported | 5.0 V TTL/CMOS, 3.3 V PCI-compatible | — |
| Operating Temperature (Commercial) | 0 °C to +70 °C | — |
| Lead-Free Finish (N suffix) | Yes (Pb-free) | — |
| Estado RoHS | ROHS3 Compliant (per fpgalink.com listing) | — |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 hours) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum Internal Frequency | — | 144.9 MHz (typical); 145 MHz (per digchip) |
| Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| Logic Family | — | CMOS, EEPROM-based |
| In-System Programmability | — | Yes (5.0 V ISP via JTAG) |
| Tipo de montaje | — | Surface Mount |
| Temperatura de funcionamiento | — | -40C to +85C (industrial) |
| JTAG (IEEE 1149.1) | — | Yes |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free / RoHS status not in provided data] |