EPM9560RC304-15 vs EPM9560RC304C-3 Comparación
Comparación detallada lado a lado de EPM9560RC304-15 por Altera y EPM9560RC304C-3 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560RC304C-3 - MAX 9000 CPLD, 560 Macrocells, 304-Pin RBGGA | Altera
EPM9560RC304C-3 ObsoleteComparación de especificaciones
| Parámetro | EPM9560RC304-15 | EPM9560RC304C-3 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,40 | $95,00 |
| Device Family | MAX 9000 | — |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 212 (maximum) | 212 |
| Propagation Delay (tPD) | 15 ns (combinatorial, pin-to-pin) | — |
| Recuento de pines | 304 | 304 |
| Encapsulado | 304-pin RQFP (Plastic Quad Flat Pack) | RBGGA-304 (Ceramic Ball Grid Array) |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standard | 5.0 V TTL / PCI-compliant | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Technology Node | High-performance CMOS, EEPROM process | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial temperature grade] | 0 C to +70 C (Commercial) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Estado RoHS | [DATA_NEEDED: lead-free / RoHS compliance status] | unknown (legacy part, pre-RoHS era) |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (EPLD) |
| Macrocells (Logic Elements) | — | 560 |
| Usable Gates | — | 12,000 |
| Speed Grade | — | -3 (3 ns pin-to-pin, commercial) |
| Tensión de alimentación | — | 5 V |
| Programmability | — | In-system, non-volatile EEPROM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Logic Blocks | — | Logic Array Blocks (LABs) with PIA interconnect |