EPM9560RI208-10 vs EPM9560RI208-10N Comparación
Comparación detallada lado a lado de EPM9560RI208-10 por Intel y EPM9560RI208-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-10 | EPM9560RI208-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $67,80 | $61,75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| User I/O Pins | 212 (typical for 208-RQFP package) | — |
| Encapsulado | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PQFP) |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (Industrial) | -40C to +85C (Industrial grade, "RI" suffix) |
| Programming Interface | IEEE 1149.1 (JTAG) / ISP | — |
| Configuration Memory | EEPROM, 100 erase/program cycles | On-chip EEPROM (non-volatile) |
| Estado RoHS | ROHS3 Compliant | ROHS3 Compliant (per fpgalink) |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Architecture | — | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| User I/Os | — | 212 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Tensión de alimentación | — | 5 V |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| Nivel MSL | — | 3 (168 Hours) |