EPM9560RI208-10 vs EPM9560RI208-10N 对比

详细并排对比 EPM9560RI208-10 出自 Intel 和 EPM9560RI208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RI208-10 EPM9560RI208-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $67.80 $61.75
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 12,000
Macrocells 560 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 144 MHz —
Supply Voltage (VCCINT) 5.0 V —
User I/O Pins 212 (typical for 208-RQFP package) —
封装 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (PQFP)
安装类型 Surface Mount —
工作温度 -40 °C to +85 °C (Industrial) -40C to +85C (Industrial grade, "RI" suffix)
Programming Interface IEEE 1149.1 (JTAG) / ISP —
Configuration Memory EEPROM, 100 erase/program cycles On-chip EEPROM (non-volatile)
RoHS 状态 ROHS3 Compliant ROHS3 Compliant (per fpgalink)
湿敏等级(MSL) 3 (168 Hours) —
Lead Time 1-7 days (per fpgalink listing) —
Architecture — CMOS EEPROM-based Multiple Array MatriX (MAX)
Macro Cells — 560
Register Bits — 12,160
User I/Os — 212
Pin-to-Pin Delay — 10 ns (speed grade -10)
Maximum Frequency — 100 MHz to 125 MHz
电源电压 — 5 V
Programming Method — In-system via IEEE 1149.1 (JTAG)
MSL 等级 — 3 (168 Hours)

数据手册与资源

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