EPM9560WC208-15C vs EPM9560RC208-15 Comparación
Comparación detallada lado a lado de EPM9560WC208-15C por Altera y EPM9560RC208-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560WC208-15C | EPM9560RC208-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $178,00 | $0,00 |
| Device Family | MAX 9000 | — |
| Series | EPM9560 | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 35 | — |
| Flip-Flops | 772 | — |
| User I/O Pins | 149 | — |
| Tensión de alimentación | 3.3 V or 5 V | 5.0 V |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 16.6 ns | — |
| Process Technology | 0.35 µm CMOS EEPROM | — |
| Encapsulado | CQFP-208 (Ceramic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Operating Temperature Grade | C (Commercial) | — |
| MultiVolt I/O | Yes (3.3 V / 5 V tolerant) | — |
| Estado RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Family | — | MAX 9000 |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | — | 12,000 gates |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |