H5ANAG6NBJR-UHC vs H5ANAG6NBJR-RDC Comparación
Comparación detallada lado a lado de H5ANAG6NBJR-UHC por SK hynix y H5ANAG6NBJR-RDC por SK hynix. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | H5ANAG6NBJR-UHC | H5ANAG6NBJR-RDC |
|---|---|---|
| Marca | SK hynix | SK hynix |
| Categoría | DRAM | DRAM |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,09 | $9,60 |
| Tipo de memoria | DDR4 SDRAM | DDR4 SDRAM |
| Density | 4 Gb | 16 Gb |
| Organización de memoria | 256M x 16 | — |
| Interfaz | DDR4 (CMOS) | Synchronous, double data rate |
| Encapsulado | PBGA96 / FBGA-96 (TFBGA) | FBGA (Ball Grid Array), surface mount |
| Package Dimensions | 13 mm length (per JESD-30 R-PBGA-B96) | — |
| Access Mode | Multi Bank, Page Burst | — |
| Temperatura de funcionamiento | -40C to +95C | [DATA_NEEDED: Operating Temperature Range] |
| Refresh | Auto / Self Refresh | — |
| Data Mask | Supported (DM function) | — |
| Asynchronous Reset | Supported | — |
| On-Chip Termination | Dynamic ODT | — |
| ZQ Calibration | Supported | — |
| Write Leveling | Supported | — |
| CRC | Supported | — |
| Supply Voltage Class | DDR4 (1.2 V class) | — |
| Estado RoHS | RoHS Compliant | [DATA_NEEDED: RoHS Status] |
| REACH Compliance | Compliant | — |
| ECCN | EAR99 | — |
| HTS Code | 8542.32.00.36 | — |
| Latencia CAS | [DATA_NEEDED: CAS Latency] | — |
| Max Data Rate | [DATA_NEEDED: Max Data Rate] | — |
| Memory Organization | — | 16Gb x16 |
| Velocidad de datos | — | 2666 Mbps (speed grade -RDC) |
| Supply Voltage (VDD) | — | 1.2 V |
| Clocking | — | Fully synchronous to both clock edges |
| Tipo de montaje | — | Surface Mount |
| Technology | — | CMOS |
| Standard | — | JEDEC DDR4 SDRAM |
| Application | — | Main memory |
| On-Die Termination (ODT) | — | Supported (DDR4 feature) |
| Bank Group Architecture | — | DDR4 bank groups (per JEDEC DDR4) |