K3KL8L80QM-MUCT vs K3LKBKB0BM-MGCP Comparación
Comparación detallada lado a lado de K3KL8L80QM-MUCT por Samsung Electronics y K3LKBKB0BM-MGCP por Samsung Electronics. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Samsung Electronics
K3LKBKB0BM-MGCP - 32Gbit LPDDR5 DRAM 6400Mbps | Samsung
K3LKBKB0BM-MGCP ✓ ActivoComparación de especificaciones
| Parámetro | K3KL8L80QM-MUCT | K3LKBKB0BM-MGCP |
|---|---|---|
| Marca | Samsung Electronics | Samsung Electronics |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,40 | $46,62 |
| Tipo de memoria | LPDDR5X SDRAM | DRAM (LPDDR5 SDRAM) |
| Density | 32 Gb (4 GB) | — |
| Organización de memoria | [DATA_NEEDED: organization (xN bit width)] | 1G x 32 |
| Velocidad de datos | [DATA_NEEDED: data rate per pin (Gbps)] | 6400 Mbps per pin |
| Supply Voltage Class | [DATA_NEEDED: VDD/VDDQ voltage] | — |
| Speed Grade | QM (per Samsung part numbering) | — |
| Encapsulado | FBGA (original package, 315-ball class) | FBGA-315 |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -25C to +85C |
| Interfaz | LPDDR5X channel interface | LPDDR5 x32 |
| Series | LPDDR5X | — |
| Marca | Samsung Semiconductor | — |
| Packaging Suffix | MUCT | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Nivel MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Application Segment | Mobile / AI edge computing | Mobile, embedded, industrial computing |
| Tamaño de memoria | — | 32 Gbit |
| Supply Voltage Rails | — | 500 mV, 900 mV, 1.05 V, 1.8 V |
| Technology Generation | — | LPDDR5 (JEDEC LPDDR5 family) |
| Density per Package | — | 4 GB (32 Gbit) |
| Refresh | — | Self-refresh and auto-refresh (LPDDR5 standard) |
| Standby / Deep Sleep | — | LPDDR5 deep-sleep power states |
| Access Time / Latency | — | [DATA_NEEDED: CAS latency] |