P2010NSE2HHC vs P2020NSE2HFC Comparación
Comparación detallada lado a lado de P2010NSE2HHC por NXP Semiconductors y P2020NSE2HFC por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
P2020NSE2HFC - QorIQ P2 Dual-Core 1.2GHz SoC | NXP Semiconductors
P2020NSE2HFC ✓ ActivoComparación de especificaciones
| Parámetro | P2010NSE2HHC | P2020NSE2HFC |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Activo | Activo |
| Manufacturer | NXP Semiconductors | — |
| Part Family | QorIQ P2 (P2010/P2020) | — |
| Processor Type | PowerPC e500v2 | — |
| Core Count | 1 (single-core) | — |
| Data Path Width | 32-bit | — |
| Core Frequency | 800 MHz | — |
| Temperatura de funcionamiento | 0 C to +125 C | — |
| Memory Controller | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC |
| Ethernet | Gigabit Ethernet (multiple ports) | — |
| PCIe | Yes (PCI Express) | — |
| Serial RapidIO (SRIO) | Yes | — |
| USB | Yes (USB 2.0 with PHY) | USB 2.0 Host/Device |
| Security Engine (SEC) | Yes (AES / 3DES / SHA) | — |
| Encapsulado | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II 31x31 mm with exposed pad |
| Tipo de montaje | Surface Mount (BGA) | — |
| Estado RoHS | RoHS Compliant | Compliant |
| Lead Free Status | Lead Free | — |
| Packaging | Tray | — |
| Silicon Revision | Rev 2.1 | — |
| Family | — | QorIQ P2 |
| Core Architecture | — | PowerPC e500v2 |
| Number of Cores | — | 2 |
| Ancho del bus de datos | — | 32-bit |
| Maximum Core Frequency | — | 1.2 GHz |
| Rango de temperatura de funcionamiento | — | 0 °C to +125 °C |
| Co-Processor / Security Engine | — | SEC 3.3 (IPsec/SSL/3GPP) |
| Ethernet Interfaces | — | 10/100/1000 Mbps (RGMII), dual GbE |
| PCI Express | — | PCIe Gen 1.1 x1/x2/x4 controllers |
| Serial RapidIO | — | 2x SRIO ports |
| UART | — | 4x UART |
| I2C / SPI / SDHC | — | Yes (2x I2C, SPI, SDHC) |
| NAND Flash Controller | — | Yes |
| L1 Cache (per core) | — | 32 KB I-cache + 32 KB D-cache |
| L2 Cache (shared) | — | 512 KB |
| Tensión de alimentación | — | [DATA_NEEDED: core voltage] |