P2010NSE2HHC vs P2020NSE2HFC Vergleich
Detaillierter Direktvergleich von P2010NSE2HHC von NXP Semiconductors und P2020NSE2HFC von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
P2020NSE2HFC - QorIQ P2 Dual-Core 1.2GHz SoC | NXP Semiconductors
P2020NSE2HFC ✓ AktivSpezifikationsvergleich
| Parameter | P2010NSE2HHC | P2020NSE2HFC |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Manufacturer | NXP Semiconductors | — |
| Part Family | QorIQ P2 (P2010/P2020) | — |
| Processor Type | PowerPC e500v2 | — |
| Core Count | 1 (single-core) | — |
| Data Path Width | 32-bit | — |
| Core Frequency | 800 MHz | — |
| Betriebstemperatur | 0 C to +125 C | — |
| Memory Controller | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC |
| Ethernet | Gigabit Ethernet (multiple ports) | — |
| PCIe | Yes (PCI Express) | — |
| Serial RapidIO (SRIO) | Yes | — |
| USB | Yes (USB 2.0 with PHY) | USB 2.0 Host/Device |
| Security Engine (SEC) | Yes (AES / 3DES / SHA) | — |
| Gehäuse | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II 31x31 mm with exposed pad |
| Montageart | Surface Mount (BGA) | — |
| RoHS-Status | RoHS Compliant | Compliant |
| Lead Free Status | Lead Free | — |
| Packaging | Tray | — |
| Silicon Revision | Rev 2.1 | — |
| Family | — | QorIQ P2 |
| Core Architecture | — | PowerPC e500v2 |
| Number of Cores | — | 2 |
| Datenbusbreite | — | 32-bit |
| Maximum Core Frequency | — | 1.2 GHz |
| Betriebstemperaturbereich | — | 0 °C to +125 °C |
| Co-Processor / Security Engine | — | SEC 3.3 (IPsec/SSL/3GPP) |
| Ethernet Interfaces | — | 10/100/1000 Mbps (RGMII), dual GbE |
| PCI Express | — | PCIe Gen 1.1 x1/x2/x4 controllers |
| Serial RapidIO | — | 2x SRIO ports |
| UART | — | 4x UART |
| I2C / SPI / SDHC | — | Yes (2x I2C, SPI, SDHC) |
| NAND Flash Controller | — | Yes |
| L1 Cache (per core) | — | 32 KB I-cache + 32 KB D-cache |
| L2 Cache (shared) | — | 512 KB |
| Versorgungsspannung | — | [DATA_NEEDED: core voltage] |