P5020NSN1QMB557 vs P5010NSN1QMB Comparación
Comparación detallada lado a lado de P5020NSN1QMB557 por NXP Semiconductors y P5010NSN1QMB por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
P5020NSN1QMB557 - QorIQ Dual-Core 1.6GHz SoC | NXP | Networking
P5020NSN1QMB557 ✓ ActivoNXP Semiconductors
P5010NSN1QMB - QorIQ P5010 SoC, 64-bit Power Arch, 2.0GHz, 1295-FCBGA | NXP
P5010NSN1QMB ✓ ActivoComparación de especificaciones
| Parámetro | P5020NSN1QMB557 | P5010NSN1QMB |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $995,00 | $318,25 |
| Part Number | P5020NSN1QMB557 | — |
| Manufacturer | NXP Semiconductors | — |
| Series | QorIQ P5 | — |
| Core Architecture | Power Architecture e5500 (64-bit) | — |
| Number of Cores | 2 | — |
| Core Frequency | 1.6 GHz (max per part decoder NSN1) | — |
| Rango de temperatura de funcionamiento | 0 C to 105 C (extended grade) | — |
| Encryption | No encryption (NoEnc per decoder M) | Hardware-accelerated |
| DDR Memory Controller | DDR3 with ECC, 64-bit | — |
| PCIe Interface | PCIe Gen2 (per QorIQ P5020 datasheet family) | — |
| Ethernet | Gigabit Ethernet (GbE) interfaces | Dual Gigabit Ethernet |
| Serial I/O | Serial RapidIO (SRIO) | — |
| Hardware Acceleration | Pattern-match / trusted-execution engine | DPAA (Data Path Acceleration Architecture) engine |
| Encapsulado | 1295-ball FCPBGA 37.5x37.5 mm | 1295-FCBGA (37.5 x 37.5 mm) |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Architecture | — | Power Architecture e5500 (64-bit) |
| Core Count | — | 1 core |
| Maximum Core Frequency | — | 2.0 GHz |
| Cache (L1 Instruction per core) | — | 32 KB |
| Cache (L1 Data per core) | — | 32 KB |
| Cache (L2 shared frontside) | — | 1 MB |
| Memory Controller | — | DDR3 with ECC support |
| PCIe | — | PCI Express Gen 2 controllers integrated |
| High-Speed Interconnect | — | Serial RapidIO (SRIO) |
| Security Engine | — | SEC crypto engine integrated |
| Temperatura de funcionamiento | — | 0C to +105C |