RTAX2000D-CQ352B vs RTAX2000D-1CQ352B Comparación
Comparación detallada lado a lado de RTAX2000D-CQ352B por Microsemi y RTAX2000D-1CQ352B por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Microsemi
RTAX2000D-CQ352B - 2M-Gate Rad-Tolerant FPGA, CQFP-352 | Microchip
RTAX2000D-CQ352B ✓ ActivoMicrochip Technology
RTAX2000D-1CQ352B - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000D-1CQ352B ✓ ActivoComparación de especificaciones
| Parámetro | RTAX2000D-CQ352B | RTAX2000D-1CQ352B |
|---|---|---|
| Marca | Microsemi | Microchip Technology |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3.100,00 | $3.120,00 |
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | RTAX-S/SL and RTAX-DSP (RTAX2000D) |
| Equivalent System Gates | 2000000 | 2,000,000 |
| Logic Cells | 29568 | — |
| CLBs | 19712 | — |
| Core Supply Voltage | 1.5 V nominal (1.425 V to 1.575 V) | 1.5 V nominal (1.425 V to 1.575 V) |
| Process Technology | CMOS antifuse | — |
| Configuration Type | One-time programmable antifuse, live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Up to 540 kbits SRAM with optional EDAC |
| Clocking Features | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Carry logic | — |
| Encapsulado | CQFP-352 ceramic quad flat pack | 352-pin Ceramic Column Grid Array (CQ352) |
| Screening / Speed Grade | B (burn-in screening); D suffix = tighter ICCA limits at 125C final test | — |
| Tipo de montaje | Surface Mount | Surface Mount (ceramic column grid array) |
| Application Domain | Space-flight systems | Space-flight, radiation-tolerant |
| Radiation Tolerance | Radiation-tolerant (TID/SEE per family datasheet) | — |
| Estado RoHS | [DATA_NEEDED: RoHS Status] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: Operating Temperature Range] | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O Bank Supply Voltage] | — |
| Maximum User I/O | [DATA_NEEDED: Maximum User I/O Count] | — |
| Technology | — | Antifuse (nonvolatile), Digital CMOS |
| CLBs (Logic Cells) | — | 19,712 CLBs / 29,568 logic cells (per family organization) |
| DSP Mathblocks | — | Up to 120 (18-bit x 18-bit MAC) |
| DSP Performance | — | 125 MHz 18-bit x 18-bit multiply-accumulate |
| Total Ionizing Dose | — | 300 krad (Si) functional / 200 krad (Si) with operation |
| Speed Grade | — | -1 |
| Temperature Range | — | Commercial (C) |
| Configuration | — | Live at power-up, no external configuration device (antifuse) |
| Routing Features | — | Segmentable clocks, chip-wide highway routing, carry logic |
| Embedded SRAM Features | — | Built-in FIFO control logic |