RTAX2000D-CQ352B vs RTAX2000D-1CQ352B Comparison
Detailed side-by-side comparison of RTAX2000D-CQ352B by Microsemi and RTAX2000D-1CQ352B by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microsemi
RTAX2000D-CQ352B - 2M-Gate Rad-Tolerant FPGA, CQFP-352 | Microchip
RTAX2000D-CQ352B ✓ ActiveMicrochip Technology
RTAX2000D-1CQ352B - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000D-1CQ352B ✓ ActiveSpecification Comparison
| Parameter | RTAX2000D-CQ352B | RTAX2000D-1CQ352B |
|---|---|---|
| Brand | Microsemi | Microchip Technology |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3,100.00 | $3,120.00 |
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | RTAX-S/SL and RTAX-DSP (RTAX2000D) |
| Equivalent System Gates | 2000000 | 2,000,000 |
| Logic Cells | 29568 | — |
| CLBs | 19712 | — |
| Core Supply Voltage | 1.5 V nominal (1.425 V to 1.575 V) | 1.5 V nominal (1.425 V to 1.575 V) |
| Process Technology | CMOS antifuse | — |
| Configuration Type | One-time programmable antifuse, live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Up to 540 kbits SRAM with optional EDAC |
| Clocking Features | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Carry logic | — |
| Package | CQFP-352 ceramic quad flat pack | 352-pin Ceramic Column Grid Array (CQ352) |
| Screening / Speed Grade | B (burn-in screening); D suffix = tighter ICCA limits at 125C final test | — |
| Mounting Type | Surface Mount | Surface Mount (ceramic column grid array) |
| Application Domain | Space-flight systems | Space-flight, radiation-tolerant |
| Radiation Tolerance | Radiation-tolerant (TID/SEE per family datasheet) | — |
| RoHS Status | [DATA_NEEDED: RoHS Status] | — |
| Operating Temperature | [DATA_NEEDED: Operating Temperature Range] | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O Bank Supply Voltage] | — |
| Maximum User I/O | [DATA_NEEDED: Maximum User I/O Count] | — |
| Technology | — | Antifuse (nonvolatile), Digital CMOS |
| CLBs (Logic Cells) | — | 19,712 CLBs / 29,568 logic cells (per family organization) |
| DSP Mathblocks | — | Up to 120 (18-bit x 18-bit MAC) |
| DSP Performance | — | 125 MHz 18-bit x 18-bit multiply-accumulate |
| Total Ionizing Dose | — | 300 krad (Si) functional / 200 krad (Si) with operation |
| Speed Grade | — | -1 |
| Temperature Range | — | Commercial (C) |
| Configuration | — | Live at power-up, no external configuration device (antifuse) |
| Routing Features | — | Segmentable clocks, chip-wide highway routing, carry logic |
| Embedded SRAM Features | — | Built-in FIFO control logic |