XC3090L-8PCG84I vs XC3090L-8PCG84C Comparación
Comparación detallada lado a lado de XC3090L-8PCG84I por Xilinx y XC3090L-8PCG84C por Xilinx. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | XC3090L-8PCG84I | XC3090L-8PCG84C |
|---|---|---|
| Marca | Xilinx | Xilinx |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $61,75 | $26,10 |
| Family | XC3000L Low-Voltage Field Programmable Gate Array | XC3000A/L Series FPGA |
| Usable Gates | 6,000 | — |
| Configurable Logic Blocks (CLBs) | 320 | — |
| User I/O Pins | 70 | 70 (maximum) |
| Tensión de alimentación | 3.3 V | — |
| Maximum Toggle Frequency | 80 MHz | — |
| Speed Grade | -8 | -8 (moderate) |
| Encapsulado | 84-pin PLCC (PCG84) | 84-pin PLCC (J-Lead, PCG84) |
| Tipo de montaje | Through-Hole (PLCC socket) | Surface Mount (PLCC J-Lead) |
| Temperatura de funcionamiento | -40 °C to +85 °C (Industrial) | 0 C to +70 C (commercial 'C' suffix) |
| Configuration Memory | SRAM (volatile, reload required at power-up) | — |
| Process Technology | CMOS SRAM-based FPGA | [DATA_NEEDED: process node] |
| I/O Standards | TTL, CMOS | — |
| Estado RoHS | [DATA_NEEDED: rohs compliance for legacy PLCC variant] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status for PCG84 PLCC package] | unknown |
| Development Tool | XACT (Xilinx Classic), XC3000 design flow | — |
| Programmable Elements | IOBs, CLBs, Programmable Interconnect | — |
| Boundary Scan | Yes (per XC3000 family) | — |
| Logic Cells / CLBs | — | 70 Configurable Logic Blocks |
| Gate Count | — | 6,400 gates (typical) |
| Configuration Program Store | — | 64,160 bits |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Configuration Modes | — | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Configuration Clock Range | — | [DATA_NEEDED: CCLK frequency range] |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Technology | — | SRAM-based, in-system reconfigurable |