XC3090L-8PCG84I vs XC3090L-8PCG84C Сравнение
Подробное сравнение бок о бок XC3090L-8PCG84I от Xilinx и XC3090L-8PCG84C от Xilinx. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Xilinx
XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family
XC3090L-8PCG84C ⚠ Последняя закупкаСравнение характеристик
| Параметр | XC3090L-8PCG84I | XC3090L-8PCG84C |
|---|---|---|
| Бренд | Xilinx | Xilinx |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Последняя закупка |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $61,75 | $26,10 |
| Family | XC3000L Low-Voltage Field Programmable Gate Array | XC3000A/L Series FPGA |
| Usable Gates | 6,000 | — |
| Configurable Logic Blocks (CLBs) | 320 | — |
| User I/O Pins | 70 | 70 (maximum) |
| Напряжение питания | 3.3 V | — |
| Maximum Toggle Frequency | 80 MHz | — |
| Speed Grade | -8 | -8 (moderate) |
| Корпус | 84-pin PLCC (PCG84) | 84-pin PLCC (J-Lead, PCG84) |
| Тип монтажа | Through-Hole (PLCC socket) | Surface Mount (PLCC J-Lead) |
| Рабочая температура | -40 °C to +85 °C (Industrial) | 0 C to +70 C (commercial 'C' suffix) |
| Configuration Memory | SRAM (volatile, reload required at power-up) | — |
| Process Technology | CMOS SRAM-based FPGA | [DATA_NEEDED: process node] |
| I/O Standards | TTL, CMOS | — |
| Статус RoHS | [DATA_NEEDED: rohs compliance for legacy PLCC variant] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status for PCG84 PLCC package] | unknown |
| Development Tool | XACT (Xilinx Classic), XC3000 design flow | — |
| Programmable Elements | IOBs, CLBs, Programmable Interconnect | — |
| Boundary Scan | Yes (per XC3000 family) | — |
| Logic Cells / CLBs | — | 70 Configurable Logic Blocks |
| Gate Count | — | 6,400 gates (typical) |
| Configuration Program Store | — | 64,160 bits |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Configuration Modes | — | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Configuration Clock Range | — | [DATA_NEEDED: CCLK frequency range] |
| Уровень MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Technology | — | SRAM-based, in-system reconfigurable |