XC3090L-8PCG84I vs XC3090L-8PCG84C Comparaison
Comparaison détaillée côte à côte de XC3090L-8PCG84I par Xilinx et XC3090L-8PCG84C par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090L-8PCG84I | XC3090L-8PCG84C |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $61,75 | $26,10 |
| Family | XC3000L Low-Voltage Field Programmable Gate Array | XC3000A/L Series FPGA |
| Usable Gates | 6,000 | — |
| Configurable Logic Blocks (CLBs) | 320 | — |
| User I/O Pins | 70 | 70 (maximum) |
| Tension d'alimentation | 3.3 V | — |
| Maximum Toggle Frequency | 80 MHz | — |
| Speed Grade | -8 | -8 (moderate) |
| Boîtier | 84-pin PLCC (PCG84) | 84-pin PLCC (J-Lead, PCG84) |
| Type de montage | Through-Hole (PLCC socket) | Surface Mount (PLCC J-Lead) |
| Température de fonctionnement | -40 °C to +85 °C (Industrial) | 0 C to +70 C (commercial 'C' suffix) |
| Configuration Memory | SRAM (volatile, reload required at power-up) | — |
| Process Technology | CMOS SRAM-based FPGA | [DATA_NEEDED: process node] |
| I/O Standards | TTL, CMOS | — |
| Statut RoHS | [DATA_NEEDED: rohs compliance for legacy PLCC variant] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status for PCG84 PLCC package] | unknown |
| Development Tool | XACT (Xilinx Classic), XC3000 design flow | — |
| Programmable Elements | IOBs, CLBs, Programmable Interconnect | — |
| Boundary Scan | Yes (per XC3000 family) | — |
| Logic Cells / CLBs | — | 70 Configurable Logic Blocks |
| Gate Count | — | 6,400 gates (typical) |
| Configuration Program Store | — | 64,160 bits |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Configuration Modes | — | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Configuration Clock Range | — | [DATA_NEEDED: CCLK frequency range] |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Technology | — | SRAM-based, in-system reconfigurable |