ADS5481IRGC25 - 16-Bit 80MSPS ADC w/ Buffered Input | Texas Instruments
N.º de pieza: ADS5481IRGC25 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $78.5 | $78,50 |
| 10 | $71.2 | $712,00 |
| 100 | $63.4 | $6.340,00 |
| 500 | $56.1 | $28.050,00 |
| 1.000 | $49.85 | $49.850,00 |
ADS5481IRGC25 Descripción general
A pipelined ADC is a high-speed converter architecture that uses multiple low-resolution flash stages cascaded in series; each stage resolves a few bits, then passes the residue to the next stage, producing N bits of resolution at sample rates from tens of MSPS to hundreds of MSPS. The ADS5481 belongs to the broader data-converter (ADC/DAC) IC family, which sits within the signal-chain category of mixed-signal semiconductors.
Key features include 16-bit resolution at 80 MSPS, an internal high-impedance analog input buffer that eases front-end driver design, LVDS digital outputs for low-noise data transfer, and excellent SFDR (spurious-free dynamic range) for wideband IF-sampling and baseband digitisation. The buffered input removes the kickback and settling issues typically associated with switched-capacitor ADC inputs, allowing operation behind higher-impedance filter networks.
The converter uses a multi-stage differential pipeline with proprietary calibration to achieve low distortion and stable performance across the industrial temperature range. The internal buffer and reference-voltage circuitry reduce the external component count, simplifying board layout for high-density designs.
Typical applications include communications receivers, radar and electronic-warfare signal processing, test and measurement instrumentation, medical imaging front ends, and high-speed data acquisition systems where both wide bandwidth and high spurious-free dynamic range are required.
When designing with this part, pay close attention to LVDS bus length matching, decoupling on both 5 V and 3.3 V rails, and the analog-input network. Because the input is buffered, anti-alias filter design is more forgiving than with unbuffered switched-capacitor ADCs.
This page synthesises distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, providing an information-gain summary aimed at engineers evaluating the ADS5481IRGC25 for new designs or legacy second-source qualification.
Alternativas directas para ADS5481IRGC25 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con ADS5481IRGC25 (mismo factor de forma y huella) — difiere en Input Type, Package, Resolution, Number of Channels, Analog Supply Voltage.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
ADS5481IRGCR
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
ADS5482IRGC25
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
ADS5483IRGC25
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
ADS62P48IRGC25
✅ Sustitución directa✓ En stock
$49.2 / unidad
Ver hoja de datos →ADS62P23IRGC25
✅ Sustitución directa✓ En stock
$18.85 / unidad
Ver hoja de datos →ADS62P22IRGC25
✅ Sustitución directa✓ En stock
$15.5 / unidad
Ver hoja de datos →ADS5481IRGC25 Valores máximos y características eléctricas
| Resolución | 16 bit |
| Sample Rate | 80 MSPS |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Input Type | Buffered Analog, Differential |
| Digital Output Type | LVDS |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 3.3 V |
| Temperatura de funcionamiento | -40 C to +85 C |
| Encapsulado | 64-VQFN (RGC) 9x9 mm |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Compliant |
Configuración de pines de ADS5481IRGC25
| Pin 1 | AVDD — 5 V analog supply |
| Pin 2 | GND — Analog ground |
| Pin 3 | INP — Positive analog input |
| Pin 4 | INN — Negative analog input |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | VREF — Internal reference decoupling |
| Pin 7 | REFT — Top reference decoupling |
| Pin 8 | REFB — Bottom reference decoupling |
| Pin 9 | AVDD — 5 V analog supply |
| Pin 10 | GND — Analog ground |
| Pin 11 | CLK+ — Differential clock positive input |
| Pin 12 | CLK- — Differential clock negative input |
| Pin 13 | CLKDIV — Clock divide control |
| Pin 14 | RESET — Active-low reset |
| Pin 15 | PD — Active-low power-down |
| Pin 16 | OE — Output enable, active-high |
| Pin 17 | DRVDD — 3.3 V digital driver supply |
| Pin 18 | DRGND — Digital driver ground |
| Pin 19 | D0+ — LVDS data output bit 0 positive |
| Pin 20 | D0- — LVDS data output bit 0 negative |
| Pin 21 | D1+ — LVDS data output bit 1 positive |
| Pin 22 | D1- — LVDS data output bit 1 negative |
| Pin 23 | D2+ — LVDS data output bit 2 positive |
| Pin 24 | D2- — LVDS data output bit 2 negative |
| Pin 25 | D3+ — LVDS data output bit 3 positive |
| Pin 26 | D3- — LVDS data output bit 3 negative |
| Pin 27 | D4+ — LVDS data output bit 4 positive |
| Pin 28 | D4- — LVDS data output bit 4 negative |
| Pin 29 | D5+ — LVDS data output bit 5 positive |
| Pin 30 | D5- — LVDS data output bit 5 negative |
| Pin 31 | D6+ — LVDS data output bit 6 positive |
| Pin 32 | D6- — LVDS data output bit 6 negative |
| Pin 33 | D7+ — LVDS data output bit 7 positive |
| Pin 34 | D7- — LVDS data output bit 7 negative |
| Pin 35 | D8+ — LVDS data output bit 8 positive |
| Pin 36 | D8- — LVDS data output bit 8 negative |
| Pin 37 | D9+ — LVDS data output bit 9 positive |
| Pin 38 | D9- — LVDS data output bit 9 negative |
| Pin 39 | D10+ — LVDS data output bit 10 positive |
| Pin 40 | D10- — LVDS data output bit 10 negative |
| Pin 41 | D11+ — LVDS data output bit 11 positive |
| Pin 42 | D11- — LVDS data output bit 11 negative |
| Pin 43 | D12+ — LVDS data output bit 12 positive |
| Pin 44 | D12- — LVDS data output bit 12 negative |
| Pin 45 | D13+ — LVDS data output bit 13 positive |
| Pin 46 | D13- — LVDS data output bit 13 negative |
| Pin 47 | D14+ — LVDS data output bit 14 positive |
| Pin 48 | D14- — LVDS data output bit 14 negative |
| Pin 49 | D15+ — LVDS data output bit 15 positive |
| Pin 50 | D15- — LVDS data output bit 15 negative |
| Pin 51 | CLKOUT+ — LVDS clock output positive |
| Pin 52 | CLKOUT- — LVDS clock output negative |
| Pin 53 | DRVDD — 3.3 V digital driver supply |
| Pin 54 | DRGND — Digital driver ground |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | AVDD — 5 V analog supply |
| Pin 61 | GND — Analog ground |
| Pin 62 | AVDD — 5 V analog supply |
| Pin 63 | GND — Analog ground |
| Pin 64 | EP — Exposed thermal pad, ground |
Aplicaciones típicas
ADS5481IRGC25 es adecuado para 6 aplicacións: Communications Receiver IF Sampling, Radar and Electronic Warfare Signal Processing, Test and Measurement Instrumentation, Medical Imaging Front End, Industrial Data Acquisition Systems, Software Defined Radio (SDR) Platform.
Communications Receiver IF Sampling
The ADS5481IRGC25 fits communications receiver IF-sampling designs because its 16-bit resolution at 80 MSPS captures narrowband signals with wide dynamic range, while the buffered analog input removes the kickback of switched-capacitor ADCs and tolerates higher source impedance from the anti-alias filter. Placed after the SAW or LC IF filter, the converter digitises the IF at 80 MSPS for digital down-conversion in an FPGA or DSP, replacing a multi-stage analog demodulator chain. Unlike unbuffered ADC inputs, the ADS5481's input buffer maintains SFDR at higher IF frequencies, enabling software-defined-radio architectures. With LVDS outputs, the digital interface remains low-EMI and easily routed across FR-4 to the host processor.
Recomendado
Radar and Electronic Warfare Signal Processing
The ADS5481IRGC25 is well matched to radar and electronic-warfare receivers because of its 16-bit resolution at 80 MSPS with high SFDR, which preserves the spurious-free window needed to detect small returns next to large clutter returns. In a typical radar front end, the buffered input accepts the IF signal directly from a log-amp or limiter output without an external buffer amplifier, simplifying the BOM. Compared to a 14-bit ADC running at the same rate, the additional 2 bits of resolution extend dynamic range by ~12 dB, which is critical in dense-target environments. The LVDS digital output keeps emissions low, important for co-located receiver and transmitter paths.
Recomendado
Test and Measurement Instrumentation
The ADS5481IRGC25 suits high-end oscilloscopes, spectrum analyzers, and arbitrary-waveform digitizers that demand 16-bit vertical resolution at high sample rates. Its buffered analog input allows direct connection to a wideband front-end attenuator and preamplifier chain, removing the need for a dedicated ADC driver and improving noise figure. In a digitizer card, the converter runs at 80 MSPS to oversample the input, which pushes quantisation noise below the instrument noise floor. Compared to 12-bit oscilloscope ADCs, the 16-bit ADS5481 delivers 16x more vertical codes, enabling wider dynamic range and lower harmonic distortion measurements in compliance-test applications.
Recomendado
Medical Imaging Front End
The ADS5481IRGC25 is used in medical-imaging systems such as ultrasound beamformers, CT scanners, and digital X-ray detector readouts where 16-bit dynamic range captures the full echo or attenuation range. The buffered input minimises distortion when driving the ADC from high-impedance transducer or photodiode preamp outputs, while 80 MSPS sample rate supports real-time imaging data rates. In an ultrasound system, multiple ADS5481 channels can be synchronised for parallel beamformer paths, all sharing a common clock to maintain phase coherence. Compared to 12-bit medical ADCs, the additional 4 bits of resolution increase the number of useful grayscale steps, improving diagnostic image quality.
Recomendado
Industrial Data Acquisition Systems
The ADS5481IRGC25 supports high-speed industrial data-acquisition systems that need 16-bit accuracy for vibration, acoustic, or strain-gauge digitisation. The buffered input works directly with piezoelectric sensors and instrumentation amplifiers, removing the load-induced distortion that plagues unbuffered switched-capacitor ADCs. With 80 MSPS, the converter easily oversamples 20 kHz mechanical vibration bands, allowing digital filtering and FFT analysis at the host. Compared to 14-bit industrial ADCs, the additional 2 bits lower the noise floor and improve spurious-free dynamic range, important for predictive-maintenance and condition-monitoring applications.
Recomendado
Software Defined Radio (SDR) Platform
The ADS5481IRGC25 enables wideband software-defined-radio platforms that digitise a swath of spectrum for digital channelisation in an FPGA. Its 80 MSPS sample rate covers up to 40 MHz of instantaneous bandwidth, while 16-bit resolution preserves modulation accuracy for sensitive waveforms such as QAM-1024 and LTE signals. The buffered analog input accepts the output of a wideband RF front end with minimal loading, preserving gain and phase response. Compared to a 12-bit SDR ADC, the 16-bit ADS5481 reduces quantisation noise by 16 dB, directly improving receiver sensitivity. The LVDS interface simplifies PCB routing to the host FPGA's LVDS receiver pins.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para ADS5481IRGC25 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | ADS5481IRGCR | ADS5482IRGC25 | ADS5483IRGC25 | ADS62P48IRGC25 |
|---|---|---|---|---|---|
| Package | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit |
| Sample Rate | 80 MSPS | 80 MSPS | 105 MSPS | 135 MSPS | 210 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Input Type | Buffered Differential | Buffered Differential | Buffered Differential | Buffered Differential | Buffered Differential |
| Digital Output | LVDS | LVDS | LVDS | LVDS | LVDS |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 3.3 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Diferenciadores clave
- Buffered analog input removes driver amplifier requirement (frente a ADS62P48IRGC25)
- 16-bit resolution with 80 MSPS in same family footprint (frente a ADS5483IRGC25)
- Industrial temperature range and proven TI supply continuity (frente a ADS62P22IRGC25)
Notas de diseño
Estimated: the ADS5481 draws approximately 600 mW from the 5 V analog supply and 200 mW from the 3.3 V digital supply at 80 MSPS. Place 0.1 uF X7R ceramic decoupling capacitors as close as possible to each AVDD and DRVDD pin, with a single 10 uF bulk tantalum or polymer capacitor near the analog supply entry point. Star-ground the analog and digital ground returns at the exposed thermal pad to prevent digital return currents from coupling into the analog input network.
Route the LVDS output pairs as 100 ohm differential microstrip lines on the top layer over a continuous ground plane, with intra-pair length matching of better than 150 mil and inter-pair length matching of better than 300 mil. Keep total length below 6 inches to preserve data-eye margin. Place the LVDS receiver pins on the FPGA within 4 inches of the ADC. The 80 MHz LVDS clock pair requires tighter matching (better than 50 mil) and should be isolated from the data pairs by at least 3W spacing.
Drive the ADC clock input with a low-jitter, differential source such as a dedicated clock jitter cleaner. According to the TI datasheet, the SNR degrades by approximately 1 dB for every 1 ps of RMS clock jitter at 80 MSPS. Use an LVDS or LVPECL driver, AC-couple the clock pair with 0.1 uF capacitors, and bias the inputs to the common-mode voltage specified in the datasheet. A poor clock source is the single most common cause of poor SNR in ADC system design.
Solder the exposed thermal pad (EP) to a continuous ground copper pour on the top layer, with at least 8 thermal vias (0.3 mm drill) connecting the top pad to an internal ground plane. Estimated: this arrangement keeps theta_JA near 28 C/W, allowing the 800 mW total dissipation to limit the junction-to-ambient temperature rise to approximately 22 C. In enclosed enclosures with limited airflow, derate the maximum ambient temperature by 10-15 C.
Avoid routing the analog input traces on the same layer as digital outputs or clock signals. The buffered analog input is high-impedance, so any capacitive coupling from the digital side can inject noise that appears as spurious content in the ADC output spectrum. Use a guard trace tied to analog ground on both sides of the analog input microstrip. Do not omit the VCM decoupling capacitor; it provides the reference for the common-mode output that biases the input driver stage.
Información de cumplimiento
RoHS compliant per TI product page. The ADS5481IRGC25 is an industrial-grade part (not AEC-Q100 automotive); for automotive applications, contact TI for the appropriate Q1-grade part number.
