DP83867E - Gigabit Ethernet PHY, RGMII/SGMII, 48-VQFN | TI
N.º de pieza: DP83867E ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $8.42 | $8,42 |
| 10 | $7.65 | $76,50 |
| 100 | $6.95 | $695,00 |
| 500 | $6.2 | $3.100,00 |
| 1.000 | $5.55 | $5.550,00 |
DP83867E Descripción general
An Ethernet PHY (Physical Layer transceiver) is a mixed-signal IC that connects a MAC controller to the copper medium (twisted-pair cable), handling line encoding/decoding, link training, echo/next-crosstalk cancellation, and clock/data recovery across the MDI. The DP83867E sits at the bottom of the OSI physical layer, translating digital MAC frames into analog baseband signals on the cable. In the taxonomy: Ethernet PHY -> transceiver -> network interface IC -> communication semiconductor. The part exceeds 8 kV IEC 61000-4-2 ESD on the cable pins, making it a robust choice for industrial and automotive-grade Ethernet links.
Key features include support for both RGMII and SGMII MAC interfaces, integrated 1.25 GHz SerDes for SGMII, low-power 1000BASE-T operation, programmable LED outputs, and a flexible MDIO/MDC management interface. The extended-temperature grade (-40C to +105C ambient with proper thermal design) targets industrial control, factory automation, and outdoor equipment where commercial-grade PHYs derate.
Architecturally, the DP83867E uses a DSP-based echo and crosstalk canceller, an integrated 1000BASE-T PMA/PMD with on-chip termination, and a low-jitter PLL to recover the 125 MHz reference. The SGMII variant routes the recovered data over a 1.25 Gbps differential serial link, eliminating the 12-bit parallel RGMII bus and reducing board-layer routing complexity in space-constrained SoMs.
Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), factory-floor IO modules, motor drives, telecom base-station routers, and automotive Ethernet PHYs for in-vehicle networking. The SGMII interface in particular suits SoCs that place the PHY on a remote daughter card or that prefer serial MAC connectivity.
Design consideration: the MDI traces require 100-ohm controlled differential impedance and an integrated magnetics RJ-45 with center-tap; the 1.0 V analog and 2.5/3.3 V digital rails must be cleanly decoupled to meet the IEEE 802.3 return-loss mask. Use the TI reference design checklist for BOM and stack-up.
This page synthesizes distributor pricing, package-accurate cross-references, and practical PCB design notes that go beyond the manufacturer datasheet to accelerate your Ethernet hardware bring-up.
Alternativas directas para DP83867E — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con DP83867E (mismo factor de forma y huella) — difiere en Package.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
DP83867ISRGZT
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DP83867CSRGZT
✅ Sustitución directa✓ En stock
$8.4 / unidad
Ver hoja de datos →DP83867ERGZR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DP83867ERGZ
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DP83867IRGZT
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DP83867CRGZT
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DP83867E Especificaciones
| Product Category | Ethernet Physical Layer Transceiver (PHY) |
| Ethernet Speed | 10/100/1000 Mbps |
| Supported Standards | 10BASE-Te, 100BASE-TX, 1000BASE-T (IEEE 802.3) |
| MAC Interface | RGMII and SGMII |
| Encapsulado | 48-VQFN (RGZ), 7x7 mm |
| Operating Temperature (Extended Grade) | -40C to +105C |
| TX Latency | < 90 ns |
| RX Latency | < 290 ns |
| ESD Protection (MDI) | Exceeds 8 kV IEC 61000-4-2 (direct contact) |
| Management Interface | MDIO / MDC |
| Estado RoHS | Compliant |
| Tipo de montaje | Surface Mount |
| Lead-Free | Yes |
| Cable Reach | 100 m on CAT5e/6 |
| Auto-Negotiation | Yes (IEEE 802.3 clauses 28, 40) |
Configuración de pines de DP83867E
| Pin 1 | TX_CLK — RGMII transmit clock output |
| Pin 2 | TX_CTRL — Transmit control (TX_EN / TX_ER multiplexed) |
| Pin 3 | TXD0 — RGMII transmit data bit 0 |
| Pin 4 | TXD1 — RGMII transmit data bit 1 |
| Pin 5 | TXD2 — RGMII transmit data bit 2 |
| Pin 6 | TXD3 — RGMII transmit data bit 3 |
| Pin 7 | VDDIO — I/O supply (2.5 V or 3.3 V) |
| Pin 8 | GND — Ground |
| Pin 9 | RX_CLK — RGMII receive clock input |
| Pin 10 | RX_CTRL — Receive control (RX_DV / RX_ER multiplexed) |
| Pin 11 | RXD0 — RGMII receive data bit 0 |
| Pin 12 | RXD1 — RGMII receive data bit 1 |
| Pin 13 | RXD2 — RGMII receive data bit 2 |
| Pin 14 | RXD3 — RGMII receive data bit 3 |
| Pin 15 | MDIO — Management data IO |
| Pin 16 | MDC — Management data clock |
| Pin 17 | INT — Interrupt output (open-drain) |
| Pin 18 | RESETn — Hardware reset (active low) |
| Pin 19 | JTAG_TDI — JTAG test data in |
| Pin 20 | JTAG_TDO — JTAG test data out |
| Pin 21 | JTAG_TMS — JTAG test mode select |
| Pin 22 | JTAG_TCK — JTAG test clock |
| Pin 23 | LED0 — Programmable LED output 0 |
| Pin 24 | LED1 — Programmable LED output 1 |
| Pin 25 | LED2 — Programmable LED output 2 |
| Pin 26 | GPIO0 — General purpose IO / strap |
| Pin 27 | GPIO1 — General purpose IO / strap |
| Pin 28 | GPIO2 — General purpose IO / strap |
| Pin 29 | CLKOUT — Reference clock output |
| Pin 30 | XI — Crystal oscillator input / ref clock |
| Pin 31 | XO — Crystal oscillator output |
| Pin 32 | VDDA1P0 — Analog 1.0 V supply |
| Pin 33 | VDDA1P0_X4 — Analog 1.0 V supply (additional) |
| Pin 34 | MDI_P0_P — Media Dependent Interface pair 0 positive |
| Pin 35 | MDI_P0_N — Media Dependent Interface pair 0 negative |
| Pin 36 | MDI_P1_P — Media Dependent Interface pair 1 positive |
| Pin 37 | MDI_P1_N — Media Dependent Interface pair 1 negative |
| Pin 38 | MDI_P2_P — Media Dependent Interface pair 2 positive |
| Pin 39 | MDI_P2_N — Media Dependent Interface pair 2 negative |
| Pin 40 | MDI_P3_P — Media Dependent Interface pair 3 positive |
| Pin 41 | MDI_P3_N — Media Dependent Interface pair 3 negative |
| Pin 42 | SGMII_SD_P — SGMII serial data positive (1.25 Gbps) |
| Pin 43 | SGMII_SD_N — SGMII serial data negative |
| Pin 44 | SGMII_REFCLK_P — SGMII reference clock positive |
| Pin 45 | SGMII_REFCLK_N — SGMII reference clock negative |
| Pin 46 | VDDIO_11 — I/O supply (additional) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
Aplicaciones típicas
DP83867E es adecuado para 7 aplicacións: Industrial Ethernet Switch, Programmable Logic Controller (PLC) Communication Module, Motor Drive Ethernet Interface, Telecom Base Station Router Line Card, Automotive In-Vehicle Networking Gateway, Test & Measurement Instrumentation, Network-Attached Storage (NAS) Controller.
Industrial Ethernet Switch
The DP83867E is the copper PHY behind each port of a multi-port industrial managed switch. Its TX latency under 90 ns and RX latency under 290 ns preserve cut-through latency budgets in real-time industrial Ethernet variants. The extended-temperature grade (-40C to +105C) supports switch line cards in factory cabinets without derating. The 8 kV IEC 61000-4-2 ESD tolerance reduces field returns from cable discharge events. Recommended: TI TPS23861 PoE controller for powered ports.
Recomendado
Programmable Logic Controller (PLC) Communication Module
PLC backplanes and remote IO modules use the DP83867E to attach to PROFINET, EtherNet/IP, or Modbus TCP networks. The SGMII interface lets a small-form-factor module place the PHY on a daughter card with minimal pin routing back to a high-density SoC. The integrated PMD/PMA removes the need for an external analog front-end, saving PCB area in DIN-rail modules. Extended-temperature operation ensures reliable boot-up in -25C unheated enclosures.
Recomendado
Motor Drive Ethernet Interface
Servo and variable-frequency drives use the DP83867E for EtherCAT, PROFINET IRT, or POWERLINK connections where deterministic latency matters. The sub-90 ns TX latency and high 8 kV ESD tolerance suit 3-phase drive panels with significant EMI and field-service handling. The RGMII bus connects cleanly to TI C2000 or third-party MCUs in the drive control board. Recommended companion: TI ISO1050 for high-side isolation if the PHY is referenced to the power-stage ground.
Recomendado
Telecom Base Station Router Line Card
5G and LTE base-station routers use the DP83867E to provide a copper 1000BASE-T backhaul or fronthaul interface alongside optical SFP ports. The SGMII mode connects the PHY to an Ethernet switch ASIC via a 1.25 Gbps serial link, freeing board layers for high-density signal routing. Industrial extended temperature and ESD robustness suit outdoor cabinet deployments. Recommended: TI TPS54331 for the 1.0 V analog rail.
Recomendado
Automotive In-Vehicle Networking Gateway
Recomendado
Test & Measurement Instrumentation
Bench-top oscilloscopes, protocol analyzers, and network test equipment use the DP83867E to expose a copper 1000BASE-T test port with high immunity to ESD from cable mating. The extended-temperature rating and high PSRR on the analog rails suit long measurement sessions in lab environments with switching supplies nearby. Recommended: TI ADC12DJ3200 for high-speed digitizer companion in protocol analyzers.
Recomendado
Network-Attached Storage (NAS) Controller
Desktop and rackmount NAS units use the DP83867E for gigabit Ethernet link aggregation to the host CPU or storage SoC. The TX/RX latency stays deterministic even with mixed bulk-transfer and IO traffic, helping maintain iSCSI/NFS throughput. The RGMII bus connects directly to the SoC's MAC, and the integrated PMD simplifies the BOM. Recommended: Marvell 88SE9235 SATA6 companion for the storage side.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para DP83867E — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | DP83867ISRGZT | DP83867CSRGZT | DP83867ERGZR | DP83867ERGZ | DP83867IRGZT | DP83867CRGZT |
|---|---|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Temperature Grade | Extended -40C to +105C | Industrial -40C to +85C | Commercial 0C to +70C | Extended -40C to +105C (same) | Extended -40C to +105C (same) | Industrial -40C to +85C | Commercial 0C to +70C |
| MAC Interface Support | RGMII + SGMII | RGMII + SGMII | RGMII only | RGMII + SGMII (same) | RGMII + SGMII (same) | RGMII only | RGMII only |
| TX Latency | < 90 ns | < 90 ns (same die) | < 90 ns (same die) | < 90 ns (same) | < 90 ns (same) | < 90 ns (same die) | < 90 ns (same die) |
| RX Latency | < 290 ns | < 290 ns (same die) | < 290 ns (same die) | < 290 ns (same) | < 290 ns (same) | < 290 ns (same die) | < 290 ns (same die) |
| ESD (MDI) | Exceeds 8 kV IEC 61000-4-2 | Exceeds 8 kV (same) | Exceeds 8 kV (same) | Exceeds 8 kV (same) | Exceeds 8 kV (same) | Exceeds 8 kV (same) | Exceeds 8 kV (same) |
| Supported Standards | 10/100/1000BASE-T (T), SGMII | 10/100/1000BASE-T, SGMII | 10/100/1000BASE-T, RGMII | 10/100/1000BASE-T, SGMII (same) | 10/100/1000BASE-T, SGMII (same) | 10/100/1000BASE-T, RGMII | 10/100/1000BASE-T, RGMII |
Diferenciadores clave
- Extended-temperature grade with RGMII + SGMII support in one part (frente a DP83867CSRGZT)
- Sub-100 ns TX latency for real-time industrial Ethernet (frente a DP83869HM)
- Pin-compatible temperature-grade family simplifies BOM risk (frente a DP83867IRGZT (industrial, no SGMII))
Notas de diseño
MDI traces between the DP83867E and the magnetics must be routed as 100-ohm differential pairs with matched length (within 50 mils) and ground shielding on both sides. Place the magnetics within 25 mm of the PHY and place the 0.1 uF / 0.001 uF MDI common-mode capacitors as close to the RJ-45 as possible. Reference the TI DP83867E datasheet layout checklist for via stitching and ground islands.
The DP83867E requires three rails: a clean 1.0 V analog rail (VDDA1P0), a 2.5 V or 3.3 V I/O rail (VDDIO), and a digital core rail. Use a ferrite bead or Pi filter to isolate the analog 1.0 V from a noisy digital 1.0 V source. Estimated: at gigabit full-duplex with 100 m cable, total IC power is roughly 0.8-1.0 W; budget at least 1.5 A capacity on the 1.0 V rail.
RGMII traces should be 50-ohm single-ended and length-matched to within 50 mils across the TX and RX groups. The TX_CLK and RX_CLK traces must be matched within 20 mils of their data group. For SGMII, the 1.25 Gbps differential pair should be 100-ohm differential with via count minimized; AC-coupling capacitors may be required between SoC and PHY.
Do not hot-plug a live Ethernet cable into an unpowered DP83867E without protection - the 8 kV ESD rating applies after PCB-mounted protection circuits are in place. Always strap the correct interface mode (RGMII vs SGMII) via GPIO strap pins at board reset before MDIO software configuration. Failing to strap correctly can lock the part in a non-responsive state.
Información de cumplimiento
RoHS and lead-free status confirmed via TI product page ti.com/product/DP83867E. Exceeds 8 kV IEC 61000-4-2 ESD per datasheet. AEC-Q100 automotive qualification should be confirmed with TI for automotive use; this part is targeted at industrial extended-temperature, not automotive Grade 1/2.
