DS90LV017M - 600Mbps Single LVDS Driver | Texas Instruments
N.º de pieza: DS90LV017M ✓ Activo| Cant. | Precio unitario | Total |
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| 1 | $0 | $0,00 |
| 10 | $0 | $0,00 |
| 100 | $0 | $0,00 |
| 500 | $0 | $0,00 |
| 1.000 | $0 | $0,00 |
DS90LV017M Descripción general
An LVDS driver is a line and bus driver that converts a low-voltage logic input into a balanced differential output. LVDS belongs to the interface IC hierarchy and uses small signal swings, common-mode biasing, and differential transmission to support high data rates while limiting electromagnetic interference. The DS90LV017M is specifically optimized for a single differential output rather than a multi-channel transceiver.
Key features include a 3.3 V supply voltage, a typical LVDS output swing of 355 mV, and a current-mode output architecture. The current-mode design helps maintain low power dissipation at high frequencies, while short-circuit fault-current limiting reduces stress during output faults. The device also supports data rates above 600 Mbps and is available in the narrow 8-pin SOIC package.
The DS90LV017M operates across the -40°C to +85°C commercial temperature range. Its 8-lead SOIC construction supports conventional surface-mount assembly and provides a practical option for interfaces requiring one LVDS transmit channel. The verified package references identify a 0.45 V-related LVDS driver specification and an 8-pin SOIC format, while several search results also associate the family with SOT-23 variants; the M suffix and supplied comparison data specifically identify DS90LV017M as the SOIC version.
Typical applications include high-speed point-to-point data links, industrial control interfaces, test equipment, instrumentation, and embedded systems that transmit clock or data signals over a short differential channel. In these systems, the driver is used with a matched LVDS receiver and controlled-impedance PCB traces.
The principal design consideration is transmission-line matching. Terminate the differential pair correctly, provide a suitable reference-plane return path, minimize stub lengths, and observe the receiver's input and termination requirements. Because the device is a single-ended-to-differential driver, system-level skew and common-mode behavior must also be checked against the receiving circuit.
This page combines the verified manufacturer and distributor specifications with package-level selection guidance, application examples, and an explicit comparison against same-family alternatives. It also distinguishes verified drop-in candidates from parts that may be electrically similar but cannot be assumed to share the DS90LV017M pinout.
Alternativas directas para DS90LV017M — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
DS90LV017ATM
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DS90LV017A
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DS90LV017ATM/NOPB
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DS90LV017M/NOPB
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DS90LV017
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DS90LV017M Especificaciones
| Device Type | Single high-speed differential line and bus driver |
| Technology | EIA-644-A and TIA-644-A LVDS |
| Tensión de alimentación | 3.3 V |
| Number of Channels | 1 |
| Maximum Data Rate | Greater than 600 Mbps |
| Equivalent Clock Frequency | Greater than 300 MHz |
| Typical Differential Output Swing | 355 mV |
| LVDS Output Voltage | 0.45 V |
| Output Architecture | Current-mode differential driver |
| Rango de temperatura de funcionamiento | -40°C to +85°C |
| Package Type | 8-lead narrow SOIC |
| Número de pines | 8 |
| Tipo de montaje | Surface mount |
| Terminal Form | Gull wing |
| Package Shape | Rectangular |
| Power Behavior | Low power dissipation at high frequency |
| Fault Protection | Minimized short-circuit fault current |
| Estado RoHS | unknown |
| REACH Status | unknown |
| AEC-Q100 Status | not_applicable |
Configuración de pines de DS90LV017M
| Pin 1 | [DATA_NEEDED: Pin 1 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
| Pin 2 | [DATA_NEEDED: Pin 2 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
| Pin 3 | [DATA_NEEDED: Pin 3 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
| Pin 4 | [DATA_NEEDED: Pin 4 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
| Pin 5 | [DATA_NEEDED: Pin 5 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
| Pin 6 | [DATA_NEEDED: Pin 6 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
| Pin 7 | [DATA_NEEDED: Pin 7 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
| Pin 8 | [DATA_NEEDED: Pin 8 name] — Exact pin assignment requires confirmation from the DS90LV017M datasheet |
Aplicaciones típicas
DS90LV017M es adecuado para 6 aplicacións: Industrial Control Point-to-Point Data Links, High-Speed Test and Measurement Instrumentation, Embedded Clock and Data Distribution, Video and Display Timing Interfaces, Networking and Backplane Clock Distribution, Medical and Diagnostic Signal Interfaces.
Industrial Control Point-to-Point Data Links
The DS90LV017M fits short industrial control-board links that need one high-speed differential transmit channel. Its 3.3 V supply and support for data rates above 600 Mbps provide ample margin for clock, command, or sampled-data transfers between controller and peripheral cards. The current-mode driver architecture is intended to keep dissipation low at high frequency, while the 8-lead narrow SOIC package simplifies conventional surface-mount assembly. In a robust implementation, route the differential pair over a continuous ground plane, preserve impedance, match the receiver termination, and isolate it from motors, relays, and switching power stages to avoid common-mode noise coupling.
Recomendado
High-Speed Test and Measurement Instrumentation
DS90LV017M is appropriate for instrumentation that distributes a clock or high-rate data signal over a short point-to-point path. The device's operation above 600 Mbps and 355 mV typical differential output swing align with low-voltage differential signaling used by high-speed test equipment. Place the driver near the source and terminate the receiver according to its datasheet rather than adding an arbitrary resistor. A continuous reference plane and closely coupled traces are important because discontinuities can create reflections that corrupt timing even when the raw data rate is supported. Verify probe loading, cable or PCB length, receiver thresholds, and edge-margin requirements across temperature.
Recomendado
Embedded Clock and Data Distribution
The DS90LV017M can transmit a single high-speed clock or data signal between tightly coupled sections of an embedded system. Its single-driver format avoids allocating multiple transmit channels when only one differential link is required, and the -40°C to +85°C range covers commercial industrial environments. The narrow SOIC package is useful where board area is constrained, although designers should still preserve controlled-impedance routing and provide the receiver's specified termination. Confirm that the source amplitude and logic thresholds are compatible with the LVDS input stage, and account for channel loss, connector parasitics, and any cable transition when extending the link beyond a board-to-board connection.
Recomendado
Video and Display Timing Interfaces
DS90LV017M may serve in proprietary video or display timing links that use a single LVDS forward channel, such as a control or synchronization path between a display controller and a panel interface. The supported rate above 600 Mbps is suitable for high-speed timing traffic, and the small 8-pin SOIC footprint helps keep the transmitter close to its source. Because the device is a driver rather than a complete video interface, the system must also supply compatible receiving logic, correct LVDS voltage levels, and a transmission medium designed for the intended distance. Validate lane timing, connector and cable losses, EMI requirements, and any display-specific protection circuitry before production use.
Recomendado
Networking and Backplane Clock Distribution
DS90LV017M is suitable for a dedicated clock or sideband channel in a compact networking or backplane subsystem when only one LVDS transmitter is required. The 3.3 V operation and high supported data rate allow the link to operate close to the driver's intended high-speed regime without using a lower-rate single-ended buffer. Use a receiver with compatible thresholds, keep the pair length matched, and provide a continuous return path to control common-mode noise. Backplane deployments should also assess connector loss, return loss, insertion loss, and crosstalk from adjacent links because the verified source data does not provide a guaranteed trace length or cable-length rating.
Recomendado
Medical and Diagnostic Signal Interfaces
The DS90LV017M can support isolated, point-to-point synchronization paths in medical monitoring equipment when the complete system satisfies the relevant safety, isolation, and electromagnetic-compatibility requirements. The driver provides one 3.3 V LVDS channel with support for rates above 600 Mbps, making it useful for transferring a local clock or high-rate sampled data between isolated sections. The component itself is not represented as AEC-Q100 qualified and has no verified medical certification in the supplied data. Engineering validation must therefore cover isolation barriers, creepage and clearance, applied-voltage limits, patient-safety architecture, grounding, and receiver behavior before clinical deployment.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para DS90LV017M — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | DS90LV017ATM | DS90LV017A | DS90LV017ATM/NOPB | DS90LV017M/NOPB | DS90LV017 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 8-lead narrow SOIC | 8-lead narrow SOIC - same | 8-lead narrow SOIC - same | 8-lead narrow SOIC - same | 8-lead narrow SOIC - same | 8-lead narrow SOIC - same |
| Device Function | Single high-speed differential LVDS driver | Single LVDS driver | Single high-speed differential driver | Single LVDS driver | Single high-speed differential LVDS driver | Single high-speed differential driver |
| Technology | EIA-644-A and TIA-644-A | LVDS | LVDS | LVDS | LVDS | LVDS |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Maximum Data Rate | Greater than 600 Mbps | Greater than 600 Mbps | Greater than 600 Mbps | Greater than 600 Mbps | Greater than 600 Mbps | Greater than 600 Mbps |
| Equivalent Clock Frequency | Greater than 300 MHz | Greater than 300 MHz | Greater than 300 MHz | Greater than 300 MHz | Greater than 300 MHz | Greater than 300 MHz |
| Typical Output Swing | 355 mV | 355 mV | 355 mV | 355 mV | 355 mV | 355 mV |
| Output Architecture | Current-mode differential driver with minimized short-circuit fault current | Current-mode LVDS driver | Current-mode LVDS driver with minimized short-circuit fault current | Current-mode LVDS driver | Current-mode LVDS driver with minimized short-circuit fault current | Current-mode LVDS driver |
Diferenciadores clave
- Exact SOIC ordering-code coverage (frente a DS90LV017ATM)
- Verified commercial-temperature operation (frente a DS90LV017ATM)
- Single-channel high-speed LVDS architecture (frente a DS90LV018ATM)
- Documented low-frequency power behavior (frente a DS90LV012ATMF)
Notas de diseño
Route the LVDS output as a tightly coupled differential pair over a continuous reference plane, with matched trace geometry and minimal vias or stubs. The verified DS90LV017M data supports rates above 600 Mbps (300 MHz), so discontinuities and reference-plane changes can produce reflections that compromise edge margin. Keep the transmitter close to the source and the receiver close to the receiver-side termination. Use the selected receiver's guidance to determine termination placement rather than adding an arbitrary resistor at the driver.
Separate the differential pair from switching-regulator loops, relay contacts, clocks, and other high-current paths to reduce common-mode and differential coupling. Maintain pair symmetry and avoid routing over split planes. If the link crosses a connector or cable transition, control impedance on both sides of the transition and provide a nearby compliant receiver termination. Exact trace dimensions were not provided in the verified data, so derive them from the PCB stack-up and the manufacturer's LVDS channel guidance.
Do not infer that every DS90LV017-family orderable code is automatically interchangeable. The supplied cross-reference data identifies DS90LV017ATM, DS90LV017A, and DS90LV017 as possible candidates, but explicitly states that datasheet and pinout checks are required. Before substitution, compare package dimensions, pin numbering, input threshold, enable polarity, differential-output polarity, supply limits, temperature range, and short-circuit behavior. Also verify that SOT-23 information attached to the broader family is not confused with the DS90LV017M 8-lead SOIC version.
Use the manufacturer's current-versus-frequency data to estimate dissipation with the actual output load and data activity. Estimated: Pdissipation is approximately equal to supply current multiplied by 3.3 V, adjusted for output and internal losses; the exact current was not supplied, so no wattage result is asserted. Validate the 8-lead SOIC at the highest expected data rate, worst-case ambient temperature, and fault condition, and preserve the manufacturer's recommended copper and airflow conditions.
Información de cumplimiento
The supplied verified data does not explicitly state RoHS, REACH, lead-free, halogen-free, or conflict-minerals compliance for DS90LV017M. AEC-Q100 is marked not applicable because no automotive qualification is identified and the cited part is a commercial-temperature interface device.
