MC68302EH20C - 20MHz M683xx 8/16-Bit MPU | NXP | 132-PQFP
N.º de pieza: MC68302EH20C ✗ Fin de vida| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $32.4 | $324,00 |
| 100 | $26.75 | $2.675,00 |
| 500 | $22.1 | $11.050,00 |
| 1.000 | $19.85 | $19.850,00 |
MC68302EH20C Descripción general
What is an M683xx microprocessor? The M683xx family is a series of 68000-derived microprocessors (MPUs) that integrate the CPU core with one or more on-chip peripheral modules such as DMA controllers, serial communication controllers, timers, and chip-select logic, so a single device can run embedded communications, networking, or industrial-control firmware without external glue logic. Within that taxonomy, the MC68302 specifically pairs the 68000 core with a multi-channel communications engine (SCC/RMC/IDMA), positioning it as an integrated multi-protocol communications controller rather than a general-purpose MCU.
Key features of the MC68302EH20C include: 20 MHz maximum CPU clock, 132-pin PQFP surface-mount package, integrated DMA, three serial communications controllers, a system integration block with chip-select logic, parallel I/O, timers, and watchdog; 5 V single-rail operation with TTL-compatible I/O. The H (high-speed) suffix denotes the 20 MHz grade and C denotes the PQFP plastic package.
Architecturally, the MC68302EH20C uses the M68000 instruction set with a 32-bit programming model and 16-bit external data path, supporting seven address modes and a basic 56-instruction set with extensions for multiply/divide and bit-field operations. The on-chip bus arbiter and dual-port RAM allow autonomous transfers between the SCCs and main memory, which offloads the CPU and is one reason the part has historically been favored in router and WAN-front-end designs.
Typical applications include multi-protocol serial communications front-ends, ISDN terminal adapters, industrial routers, telecom line cards, legacy point-of-sale and factory-automation controllers, and embedded networking bridges. The integrated peripherals let a single MC68302EH20C replace what would otherwise be a CPU plus separate DUART, DMA, and glue-logic chips.
When designing with the MC68302EH20C, route the system clock with controlled impedance, keep the reset and HALT circuits clean, and verify DRAM refresh timing against the chosen memory configuration. Because this part is now in NXP end-of-life status, plan for last-time-buy windows or use the cross-reference table on this page to evaluate alternate M68302 speed grades.
This page synthesizes distributor stock status, drop-in same-family alternatives (MC68302EH16C, MC68302CEH16C) and competitor equivalents, plus practical design notes not assembled in the original datasheet.
Alternativas directas para MC68302EH20C — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con MC68302EH20C (mismo factor de forma y huella) — difiere en Instruction Set, Maximum Clock Frequency, Data Bus Width, Package, Core.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
MC68302EH16C
✅ Sustitución directa✓ En stock
$17.1 / unidad
Ver hoja de datos →MC68302CEH16C
✅ Sustitución directa✓ En stock
$49.9 / unidad
Ver hoja de datos →MC68302EH20B
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
MC68302EH20C Valores máximos y características eléctricas
| Family | M68000 / M683xx |
| Core | M68000 (8/16-bit external data bus) |
| Number of Cores | 1 |
| Ancho del bus de datos | 8/16-bit |
| Address Bus Width | 24-bit |
| Frecuencia de reloj máxima | 20 MHz |
| Speed Grade Suffix | EH20 (20 MHz, high-speed) |
| Package Suffix | C (PQFP plastic) |
| Encapsulado | 132-PQFP (24.13 x 24.13 mm) |
| Recuento de pines | 132 |
| Tipo de montaje | Surface Mount |
| Tensión de alimentación | 5 V nominal |
| On-chip Peripherals | 3 SCC, IDMA, Chip-Select, Timers, Watchdog, Parallel I/O |
| Instruction Set | M68000 (56 base instructions + extensions) |
Configuración de pines de MC68302EH20C
| Pin 1 | A23 — Address bus bit 23 |
| Pin 2 | A22 — Address bus bit 22 |
| Pin 3 | A21 — Address bus bit 21 |
| Pin 4 | A20 — Address bus bit 20 |
| Pin 5 | A19 — Address bus bit 19 |
| Pin 6 | A18 — Address bus bit 18 |
| Pin 7 | A17 — Address bus bit 17 |
| Pin 8 | A16 — Address bus bit 16 |
| Pin 9 | A15 — Address bus bit 15 |
| Pin 10 | A14 — Address bus bit 14 |
| Pin 11 | A13 — Address bus bit 13 |
| Pin 12 | A12 — Address bus bit 12 |
| Pin 13 | A11 — Address bus bit 11 |
| Pin 14 | A10 — Address bus bit 10 |
| Pin 15 | A9 — Address bus bit 9 |
| Pin 16 | A8 — Address bus bit 8 |
| Pin 17 | A7 — Address bus bit 7 |
| Pin 18 | A6 — Address bus bit 6 |
| Pin 19 | A5 — Address bus bit 5 |
| Pin 20 | A4 — Address bus bit 4 |
| Pin 21 | A3 — Address bus bit 3 |
| Pin 22 | A2 — Address bus bit 2 |
| Pin 23 | A1 — Address bus bit 1 |
| Pin 24 | A0 — Address bus bit 0 |
| Pin 25 | D15 — Data bus bit 15 |
| Pin 26 | D14 — Data bus bit 14 |
| Pin 27 | D13 — Data bus bit 13 |
| Pin 28 | D12 — Data bus bit 12 |
| Pin 29 | D11 — Data bus bit 11 |
| Pin 30 | D10 — Data bus bit 10 |
| Pin 31 | D9 — Data bus bit 9 |
| Pin 32 | D8 — Data bus bit 8 |
| Pin 33 | D7 — Data bus bit 7 |
| Pin 34 | D6 — Data bus bit 6 |
| Pin 35 | D5 — Data bus bit 5 |
| Pin 36 | D4 — Data bus bit 4 |
| Pin 37 | D3 — Data bus bit 3 |
| Pin 38 | D2 — Data bus bit 2 |
| Pin 39 | D1 — Data bus bit 1 |
| Pin 40 | D0 — Data bus bit 0 |
| Pin 41 | VCC — +5V supply |
| Pin 42 | GND — Ground |
| Pin 43 | CLKIN — System clock input |
| Pin 44 | RESET — Reset input (active low) |
| Pin 45 | HALT — Halt input (active low) |
| Pin 46 | AS — Address Strobe |
| Pin 47 | DS — Data Strobe |
| Pin 48 | R/W — Read/Write control |
| Pin 49 | BR — Bus Request |
| Pin 50 | BG — Bus Grant |
| Pin 51 | BGACK — Bus Grant Acknowledge |
| Pin 52 | IPL0 — Interrupt Priority Level 0 |
| Pin 53 | IPL1 — Interrupt Priority Level 1 |
| Pin 54 | IPL2 — Interrupt Priority Level 2 |
| Pin 55 | FC0 — Function Code 0 |
| Pin 56 | FC1 — Function Code 1 |
| Pin 57 | FC2 — Function Code 2 |
| Pin 58 | CS0 — Chip Select 0 |
| Pin 59 | CS1 — Chip Select 1 |
| Pin 60 | CS2 — Chip Select 2 |
| Pin 61 | CS3 — Chip Select 3 |
| Pin 62 | CS4 — Chip Select 4 |
| Pin 63 | CS5 — Chip Select 5 |
| Pin 64 | CS6 — Chip Select 6 |
| Pin 65 | CS7 — Chip Select 7 |
| Pin 66 | PA0 — Parallel I/O Port A bit 0 |
| Pin 67 | PA1 — Parallel I/O Port A bit 1 |
| Pin 68 | PA2 — Parallel I/O Port A bit 2 |
| Pin 69 | PA3 — Parallel I/O Port A bit 3 |
| Pin 70 | PA4 — Parallel I/O Port A bit 4 |
| Pin 71 | PA5 — Parallel I/O Port A bit 5 |
| Pin 72 | PA6 — Parallel I/O Port A bit 6 |
| Pin 73 | PA7 — Parallel I/O Port A bit 7 |
| Pin 74 | PA8 — Parallel I/O Port A bit 8 |
| Pin 75 | PA9 — Parallel I/O Port A bit 9 |
| Pin 76 | PA10 — Parallel I/O Port A bit 10 |
| Pin 77 | PA11 — Parallel I/O Port A bit 11 |
| Pin 78 | PA12 — Parallel I/O Port A bit 12 |
| Pin 79 | PA13 — Parallel I/O Port A bit 13 |
| Pin 80 | PA14 — Parallel I/O Port A bit 14 |
| Pin 81 | PA15 — Parallel I/O Port A bit 15 |
| Pin 82 | PB0 — Parallel I/O Port B bit 0 |
| Pin 83 | PB1 — Parallel I/O Port B bit 1 |
| Pin 84 | PB2 — Parallel I/O Port B bit 2 |
| Pin 85 | PB3 — Parallel I/O Port B bit 3 |
| Pin 86 | PB4 — Parallel I/O Port B bit 4 |
| Pin 87 | PB5 — Parallel I/O Port B bit 5 |
| Pin 88 | PB6 — Parallel I/O Port B bit 6 |
| Pin 89 | PB7 — Parallel I/O Port B bit 7 |
| Pin 90 | PB8 — Parallel I/O Port B bit 8 |
| Pin 91 | PB9 — Parallel I/O Port B bit 9 |
| Pin 92 | PB10 — Parallel I/O Port B bit 10 |
| Pin 93 | PB11 — Parallel I/O Port B bit 11 |
| Pin 94 | PB12 — Parallel I/O Port B bit 12 |
| Pin 95 | PB13 — Parallel I/O Port B bit 13 |
| Pin 96 | PB14 — Parallel I/O Port B bit 14 |
| Pin 97 | PB15 — Parallel I/O Port B bit 15 |
| Pin 98 | TXD1 — SCC1 Transmit Data |
| Pin 99 | RXD1 — SCC1 Receive Data |
| Pin 100 | RTS1 — SCC1 Request To Send |
| Pin 101 | CTS1 — SCC1 Clear To Send |
| Pin 102 | CD1 — SCC1 Carrier Detect |
| Pin 103 | TXD2 — SCC2 Transmit Data |
| Pin 104 | RXD2 — SCC2 Receive Data |
| Pin 105 | RTS2 — SCC2 Request To Send |
| Pin 106 | CTS2 — SCC2 Clear To Send |
| Pin 107 | CD2 — SCC2 Carrier Detect |
| Pin 108 | TXD3 — SCC3 Transmit Data |
| Pin 109 | RXD3 — SCC3 Receive Data |
| Pin 110 | RTS3 — SCC3 Request To Send |
| Pin 111 | CTS3 — SCC3 Clear To Send |
| Pin 112 | CD3 — SCC3 Carrier Detect |
| Pin 113 | TIN1 — Timer 1 Input |
| Pin 114 | TOUT1 — Timer 1 Output |
| Pin 115 | TIN2 — Timer 2 Input |
| Pin 116 | TOUT2 — Timer 2 Output |
| Pin 117 | DREQ — IDMA Request |
| Pin 118 | DACK — IDMA Acknowledge |
| Pin 119 | DONE — IDMA Done |
| Pin 120 | VCC — +5V supply |
| Pin 121 | GND — Ground |
| Pin 122 | AVEC — Autovector |
| Pin 123 | DSACK0 — Data Transfer and Size Acknowledge 0 |
| Pin 124 | DSACK1 — Data Transfer and Size Acknowledge 1 |
| Pin 125 | BERR — Bus Error |
| Pin 126 | BR0 — Bus Request 0 |
| Pin 127 | BR1 — Bus Request 1 |
| Pin 128 | TA — Transfer Acknowledge |
| Pin 129 | TBI — Transfer Burst Inhibit |
| Pin 130 | RMC — Read-Modify-Write Cycle |
| Pin 131 | MMUDIS — MMU Disable |
| Pin 132 | VCC — +5V supply |
Aplicaciones típicas
MC68302EH20C es adecuado para 6 aplicacións: Multi-Protocol Serial Communications Front-End, Industrial Router and Bridge Controller, ISDN Terminal Adapter, Telecom Line Card and Channel Bank, Legacy Point-of-Sale Terminal, Factory-Automation Controller (Legacy).
Multi-Protocol Serial Communications Front-End
The MC68302EH20C's three on-chip Serial Communications Controllers (SCCs) and Independent DMA controller (IDMA) make it a natural fit for multi-protocol serial front-ends. Each SCC supports HDLC/SDLC, async, BISYNC, and transparent protocols, so a single 20 MHz device replaces a CPU plus three external DUARTs. In WAN-edge and serial-bridge designs the part offloads framing and DMA, leaving the M68000 core free to run routing or control firmware with no router restarts.
Recomendado
Industrial Router and Bridge Controller
Integrated chip-select logic, dual timers, parallel I/O and three SCCs let the MC68302EH20C serve as a one-chip industrial router or field-bridge controller. The on-chip peripheral integration reduces board area and BOM count versus a CPU-plus-glue design. At 20 MHz and 5 V the part delivers deterministic interrupt latency suitable for serial-field bridging on factory floors, and the watchdog timer protects unattended installations from firmware hangs.
Recomendado
ISDN Terminal Adapter
The MC68302EH20C was specifically designed for ISDN terminal-adapter and basic-rate-access designs, leveraging its three SCCs to terminate the ISDN BRI 'S' interface, drive an external codec, and maintain the D-channel signaling stack. The 20 MHz EH20C speed grade provides the throughput needed for ISDN call control plus echo-cancellation firmware, while the 5 V tolerant bus interfaces cleanly to legacy analog line interfaces.
Recomendado
Telecom Line Card and Channel Bank
Central-office line cards and channel banks historically deployed the MC68302EH20C because each SCC terminates a T1/E1 timeslot and the IDMA streams PCM samples to and from a serial backplane without CPU intervention. The 132-pin PQFP provides enough I/O for backplane glue and per-channel control, and the chip-select block can directly drive framers and codecs without external logic.
Recomendado
Legacy Point-of-Sale Terminal
POS terminals that need multiple serial ports for barcode scanners, receipt printers, and PIN pads historically use the MC68302EH20C because the three on-chip SCCs and parallel I/O handle all peripherals in a single chip. The integrated chip-select logic also drives character LCDs and keypads directly. While the part is EOL, deployed fleets continue to use it for service and repair with distributor-bonded stock.
Recomendado
Factory-Automation Controller (Legacy)
Discrete I/O, timers, and three SCCs make the MC68302EH20C a viable single-chip PLC-like controller for legacy factory-automation cells running RS-485 multi-drop fieldbuses. The 5 V supply and 132-pin PQFP remain compatible with 1990s-era backplanes, easing field-sustainment. The watchdog and chip-select block enable deterministic safety behaviors required by industrial standards of the era.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para MC68302EH20C — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | MC68302EH16C | MC68302CEH16C | MC68302EH20B |
|---|---|---|---|---|
| Package | 132-PQFP (24.13x24.13) | 132-PQFP (24.13x24.13) - same | 132-PQFP (24.13x24.13) - same | 132-PQFP (24.13x24.13) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Maximum Clock Frequency | 20 MHz | 16 MHz (-20%) | 16 MHz (-20%) | 20 MHz (same) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) |
| Data Bus Width | 8/16-bit | 8/16-bit (same) | 8/16-bit (same) | 8/16-bit (same) |
| On-chip SCCs | 3 | 3 (same) | 3 (same) | 3 (same) |
| IDMA Channels | 1 | 1 (same) | 1 (same) | 1 (same) |
| Lifecycle Status | EOL | EOL | EOL | EOL |
Diferenciadores clave
- 20 MHz speed grade within M68302 family (frente a MC68302EH16C)
- Integrated communications engine (3 SCCs + IDMA) (frente a MC68040RC40A)
- 5 V supply tolerant I/O (frente a MC68302AG16VC)
Notas de diseño
Estimated: at 20 MHz with all three SCCs and IDMA active, the MC68302EH20C dissipates roughly 0.6-0.9 W. Provide at least one solid VCC/GND pair (pin 41/42, 120/121, 132/42) with low-impedance decoupling within 5 mm of each pair. Use 0.1 uF ceramic in parallel with 10 uF tantalum bulk; a 5 V linear regulator with adequate heatsinking is recommended over a switching regulator to keep ripple on the logic supply below 50 mVpp.
Because the MC68302EH20C is EOL, do not design a new production board around this part without a written last-time-buy commitment from NXP or a bonded-stock distributor. Stock and price fluctuate week-to-week, and counterfeit risk rises sharply for any lots arriving outside authorized channels. Use only franchised distributors or vetted independent brokers with documented traceability.
The 132-pin PQFP at 20 MHz places the design in moderate-speed territory; route the address and data buses as matched-length parallel groups with a 50 ohm controlled impedance and keep traces shorter than 75 mm where possible. Series-terminate the bus with 33 ohm resistors near the MPU for heavily loaded nets. Provide a clean RESET/HALT debounce circuit and verify clock-in duty cycle stays within 40-60%.
Información de cumplimiento
Original PQFP variants from the 1990s predate RoHS - the EH20C and earlier C/EH grades are typically NOT RoHS compliant. Only later 'AG' 3.3 V variants carried RoHS marking. RoHS/REACH/AEC-Q100 status to be confirmed against the specific lot marking before qualification.
