MC68302EH20C - 20MHz M683xx 8/16-Bit MPU | NXP | 132-PQFP
部品番号: MC68302EH20C ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.4 | $324.00 |
| 100 | $26.75 | $2,675.00 |
| 500 | $22.1 | $11,050.00 |
| 1,000 | $19.85 | $19,850.00 |
MC68302EH20C 概要
What is an M683xx microprocessor? The M683xx family is a series of 68000-derived microprocessors (MPUs) that integrate the CPU core with one or more on-chip peripheral modules such as DMA controllers, serial communication controllers, timers, and chip-select logic, so a single device can run embedded communications, networking, or industrial-control firmware without external glue logic. Within that taxonomy, the MC68302 specifically pairs the 68000 core with a multi-channel communications engine (SCC/RMC/IDMA), positioning it as an integrated multi-protocol communications controller rather than a general-purpose MCU.
Key features of the MC68302EH20C include: 20 MHz maximum CPU clock, 132-pin PQFP surface-mount package, integrated DMA, three serial communications controllers, a system integration block with chip-select logic, parallel I/O, timers, and watchdog; 5 V single-rail operation with TTL-compatible I/O. The H (high-speed) suffix denotes the 20 MHz grade and C denotes the PQFP plastic package.
Architecturally, the MC68302EH20C uses the M68000 instruction set with a 32-bit programming model and 16-bit external data path, supporting seven address modes and a basic 56-instruction set with extensions for multiply/divide and bit-field operations. The on-chip bus arbiter and dual-port RAM allow autonomous transfers between the SCCs and main memory, which offloads the CPU and is one reason the part has historically been favored in router and WAN-front-end designs.
Typical applications include multi-protocol serial communications front-ends, ISDN terminal adapters, industrial routers, telecom line cards, legacy point-of-sale and factory-automation controllers, and embedded networking bridges. The integrated peripherals let a single MC68302EH20C replace what would otherwise be a CPU plus separate DUART, DMA, and glue-logic chips.
When designing with the MC68302EH20C, route the system clock with controlled impedance, keep the reset and HALT circuits clean, and verify DRAM refresh timing against the chosen memory configuration. Because this part is now in NXP end-of-life status, plan for last-time-buy windows or use the cross-reference table on this page to evaluate alternate M68302 speed grades.
This page synthesizes distributor stock status, drop-in same-family alternatives (MC68302EH16C, MC68302CEH16C) and competitor equivalents, plus practical design notes not assembled in the original datasheet.
ドロップイン代替品: MC68302EH20C — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: MC68302EH20C （同一形状・フットプリント） — 相違点: Data Bus Width, Package, Instruction Set, Maximum Clock Frequency, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
MC68302EH16C
✅ ドロップイン✓ 在庫あり
$17.1 / 個
データシートを見る →MC68302CEH16C
✅ ドロップイン✓ 在庫あり
$49.9 / 個
データシートを見る →MC68302EH20B
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
MC68302EH20C 最大定格＆電気的特性
| Family | M68000 / M683xx |
| Core | M68000 (8/16-bit external data bus) |
| Number of Cores | 1 |
| データバス幅 | 8/16-bit |
| Address Bus Width | 24-bit |
| 最大クロック周波数 | 20 MHz |
| Speed Grade Suffix | EH20 (20 MHz, high-speed) |
| Package Suffix | C (PQFP plastic) |
| パッケージ | 132-PQFP (24.13 x 24.13 mm) |
| ピン数 | 132 |
| 実装タイプ | Surface Mount |
| 電源電圧 | 5 V nominal |
| On-chip Peripherals | 3 SCC, IDMA, Chip-Select, Timers, Watchdog, Parallel I/O |
| Instruction Set | M68000 (56 base instructions + extensions) |
MC68302EH20C ピン構成
| ピン 1 | A23 — Address bus bit 23 |
| ピン 2 | A22 — Address bus bit 22 |
| ピン 3 | A21 — Address bus bit 21 |
| ピン 4 | A20 — Address bus bit 20 |
| ピン 5 | A19 — Address bus bit 19 |
| ピン 6 | A18 — Address bus bit 18 |
| ピン 7 | A17 — Address bus bit 17 |
| ピン 8 | A16 — Address bus bit 16 |
| ピン 9 | A15 — Address bus bit 15 |
| ピン 10 | A14 — Address bus bit 14 |
| ピン 11 | A13 — Address bus bit 13 |
| ピン 12 | A12 — Address bus bit 12 |
| ピン 13 | A11 — Address bus bit 11 |
| ピン 14 | A10 — Address bus bit 10 |
| ピン 15 | A9 — Address bus bit 9 |
| ピン 16 | A8 — Address bus bit 8 |
| ピン 17 | A7 — Address bus bit 7 |
| ピン 18 | A6 — Address bus bit 6 |
| ピン 19 | A5 — Address bus bit 5 |
| ピン 20 | A4 — Address bus bit 4 |
| ピン 21 | A3 — Address bus bit 3 |
| ピン 22 | A2 — Address bus bit 2 |
| ピン 23 | A1 — Address bus bit 1 |
| ピン 24 | A0 — Address bus bit 0 |
| ピン 25 | D15 — Data bus bit 15 |
| ピン 26 | D14 — Data bus bit 14 |
| ピン 27 | D13 — Data bus bit 13 |
| ピン 28 | D12 — Data bus bit 12 |
| ピン 29 | D11 — Data bus bit 11 |
| ピン 30 | D10 — Data bus bit 10 |
| ピン 31 | D9 — Data bus bit 9 |
| ピン 32 | D8 — Data bus bit 8 |
| ピン 33 | D7 — Data bus bit 7 |
| ピン 34 | D6 — Data bus bit 6 |
| ピン 35 | D5 — Data bus bit 5 |
| ピン 36 | D4 — Data bus bit 4 |
| ピン 37 | D3 — Data bus bit 3 |
| ピン 38 | D2 — Data bus bit 2 |
| ピン 39 | D1 — Data bus bit 1 |
| ピン 40 | D0 — Data bus bit 0 |
| ピン 41 | VCC — +5V supply |
| ピン 42 | GND — Ground |
| ピン 43 | CLKIN — System clock input |
| ピン 44 | RESET — Reset input (active low) |
| ピン 45 | HALT — Halt input (active low) |
| ピン 46 | AS — Address Strobe |
| ピン 47 | DS — Data Strobe |
| ピン 48 | R/W — Read/Write control |
| ピン 49 | BR — Bus Request |
| ピン 50 | BG — Bus Grant |
| ピン 51 | BGACK — Bus Grant Acknowledge |
| ピン 52 | IPL0 — Interrupt Priority Level 0 |
| ピン 53 | IPL1 — Interrupt Priority Level 1 |
| ピン 54 | IPL2 — Interrupt Priority Level 2 |
| ピン 55 | FC0 — Function Code 0 |
| ピン 56 | FC1 — Function Code 1 |
| ピン 57 | FC2 — Function Code 2 |
| ピン 58 | CS0 — Chip Select 0 |
| ピン 59 | CS1 — Chip Select 1 |
| ピン 60 | CS2 — Chip Select 2 |
| ピン 61 | CS3 — Chip Select 3 |
| ピン 62 | CS4 — Chip Select 4 |
| ピン 63 | CS5 — Chip Select 5 |
| ピン 64 | CS6 — Chip Select 6 |
| ピン 65 | CS7 — Chip Select 7 |
| ピン 66 | PA0 — Parallel I/O Port A bit 0 |
| ピン 67 | PA1 — Parallel I/O Port A bit 1 |
| ピン 68 | PA2 — Parallel I/O Port A bit 2 |
| ピン 69 | PA3 — Parallel I/O Port A bit 3 |
| ピン 70 | PA4 — Parallel I/O Port A bit 4 |
| ピン 71 | PA5 — Parallel I/O Port A bit 5 |
| ピン 72 | PA6 — Parallel I/O Port A bit 6 |
| ピン 73 | PA7 — Parallel I/O Port A bit 7 |
| ピン 74 | PA8 — Parallel I/O Port A bit 8 |
| ピン 75 | PA9 — Parallel I/O Port A bit 9 |
| ピン 76 | PA10 — Parallel I/O Port A bit 10 |
| ピン 77 | PA11 — Parallel I/O Port A bit 11 |
| ピン 78 | PA12 — Parallel I/O Port A bit 12 |
| ピン 79 | PA13 — Parallel I/O Port A bit 13 |
| ピン 80 | PA14 — Parallel I/O Port A bit 14 |
| ピン 81 | PA15 — Parallel I/O Port A bit 15 |
| ピン 82 | PB0 — Parallel I/O Port B bit 0 |
| ピン 83 | PB1 — Parallel I/O Port B bit 1 |
| ピン 84 | PB2 — Parallel I/O Port B bit 2 |
| ピン 85 | PB3 — Parallel I/O Port B bit 3 |
| ピン 86 | PB4 — Parallel I/O Port B bit 4 |
| ピン 87 | PB5 — Parallel I/O Port B bit 5 |
| ピン 88 | PB6 — Parallel I/O Port B bit 6 |
| ピン 89 | PB7 — Parallel I/O Port B bit 7 |
| ピン 90 | PB8 — Parallel I/O Port B bit 8 |
| ピン 91 | PB9 — Parallel I/O Port B bit 9 |
| ピン 92 | PB10 — Parallel I/O Port B bit 10 |
| ピン 93 | PB11 — Parallel I/O Port B bit 11 |
| ピン 94 | PB12 — Parallel I/O Port B bit 12 |
| ピン 95 | PB13 — Parallel I/O Port B bit 13 |
| ピン 96 | PB14 — Parallel I/O Port B bit 14 |
| ピン 97 | PB15 — Parallel I/O Port B bit 15 |
| ピン 98 | TXD1 — SCC1 Transmit Data |
| ピン 99 | RXD1 — SCC1 Receive Data |
| ピン 100 | RTS1 — SCC1 Request To Send |
| ピン 101 | CTS1 — SCC1 Clear To Send |
| ピン 102 | CD1 — SCC1 Carrier Detect |
| ピン 103 | TXD2 — SCC2 Transmit Data |
| ピン 104 | RXD2 — SCC2 Receive Data |
| ピン 105 | RTS2 — SCC2 Request To Send |
| ピン 106 | CTS2 — SCC2 Clear To Send |
| ピン 107 | CD2 — SCC2 Carrier Detect |
| ピン 108 | TXD3 — SCC3 Transmit Data |
| ピン 109 | RXD3 — SCC3 Receive Data |
| ピン 110 | RTS3 — SCC3 Request To Send |
| ピン 111 | CTS3 — SCC3 Clear To Send |
| ピン 112 | CD3 — SCC3 Carrier Detect |
| ピン 113 | TIN1 — Timer 1 Input |
| ピン 114 | TOUT1 — Timer 1 Output |
| ピン 115 | TIN2 — Timer 2 Input |
| ピン 116 | TOUT2 — Timer 2 Output |
| ピン 117 | DREQ — IDMA Request |
| ピン 118 | DACK — IDMA Acknowledge |
| ピン 119 | DONE — IDMA Done |
| ピン 120 | VCC — +5V supply |
| ピン 121 | GND — Ground |
| ピン 122 | AVEC — Autovector |
| ピン 123 | DSACK0 — Data Transfer and Size Acknowledge 0 |
| ピン 124 | DSACK1 — Data Transfer and Size Acknowledge 1 |
| ピン 125 | BERR — Bus Error |
| ピン 126 | BR0 — Bus Request 0 |
| ピン 127 | BR1 — Bus Request 1 |
| ピン 128 | TA — Transfer Acknowledge |
| ピン 129 | TBI — Transfer Burst Inhibit |
| ピン 130 | RMC — Read-Modify-Write Cycle |
| ピン 131 | MMUDIS — MMU Disable |
| ピン 132 | VCC — +5V supply |
主な用途
MC68302EH20C の用途: 6 件s: Multi-Protocol Serial Communications Front-End, Industrial Router and Bridge Controller, ISDN Terminal Adapter, Telecom Line Card and Channel Bank, Legacy Point-of-Sale Terminal, Factory-Automation Controller (Legacy).
Multi-Protocol Serial Communications Front-End
The MC68302EH20C's three on-chip Serial Communications Controllers (SCCs) and Independent DMA controller (IDMA) make it a natural fit for multi-protocol serial front-ends. Each SCC supports HDLC/SDLC, async, BISYNC, and transparent protocols, so a single 20 MHz device replaces a CPU plus three external DUARTs. In WAN-edge and serial-bridge designs the part offloads framing and DMA, leaving the M68000 core free to run routing or control firmware with no router restarts.
おすすめ
Industrial Router and Bridge Controller
Integrated chip-select logic, dual timers, parallel I/O and three SCCs let the MC68302EH20C serve as a one-chip industrial router or field-bridge controller. The on-chip peripheral integration reduces board area and BOM count versus a CPU-plus-glue design. At 20 MHz and 5 V the part delivers deterministic interrupt latency suitable for serial-field bridging on factory floors, and the watchdog timer protects unattended installations from firmware hangs.
おすすめ
ISDN Terminal Adapter
The MC68302EH20C was specifically designed for ISDN terminal-adapter and basic-rate-access designs, leveraging its three SCCs to terminate the ISDN BRI 'S' interface, drive an external codec, and maintain the D-channel signaling stack. The 20 MHz EH20C speed grade provides the throughput needed for ISDN call control plus echo-cancellation firmware, while the 5 V tolerant bus interfaces cleanly to legacy analog line interfaces.
おすすめ
Telecom Line Card and Channel Bank
Central-office line cards and channel banks historically deployed the MC68302EH20C because each SCC terminates a T1/E1 timeslot and the IDMA streams PCM samples to and from a serial backplane without CPU intervention. The 132-pin PQFP provides enough I/O for backplane glue and per-channel control, and the chip-select block can directly drive framers and codecs without external logic.
おすすめ
Legacy Point-of-Sale Terminal
POS terminals that need multiple serial ports for barcode scanners, receipt printers, and PIN pads historically use the MC68302EH20C because the three on-chip SCCs and parallel I/O handle all peripherals in a single chip. The integrated chip-select logic also drives character LCDs and keypads directly. While the part is EOL, deployed fleets continue to use it for service and repair with distributor-bonded stock.
おすすめ
Factory-Automation Controller (Legacy)
Discrete I/O, timers, and three SCCs make the MC68302EH20C a viable single-chip PLC-like controller for legacy factory-automation cells running RS-485 multi-drop fieldbuses. The 5 V supply and 132-pin PQFP remain compatible with 1990s-era backplanes, easing field-sustainment. The watchdog and chip-select block enable deterministic safety behaviors required by industrial standards of the era.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MC68302EH20C — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MC68302EH16C | MC68302CEH16C | MC68302EH20B |
|---|---|---|---|---|
| Package | 132-PQFP (24.13x24.13) | 132-PQFP (24.13x24.13) - same | 132-PQFP (24.13x24.13) - same | 132-PQFP (24.13x24.13) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Maximum Clock Frequency | 20 MHz | 16 MHz (-20%) | 16 MHz (-20%) | 20 MHz (same) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) |
| Data Bus Width | 8/16-bit | 8/16-bit (same) | 8/16-bit (same) | 8/16-bit (same) |
| On-chip SCCs | 3 | 3 (same) | 3 (same) | 3 (same) |
| IDMA Channels | 1 | 1 (same) | 1 (same) | 1 (same) |
| Lifecycle Status | EOL | EOL | EOL | EOL |
主な差別化要因
- 20 MHz speed grade within M68302 family （vs MC68302EH16C)
- Integrated communications engine (3 SCCs + IDMA) （vs MC68040RC40A)
- 5 V supply tolerant I/O （vs MC68302AG16VC)
設計ノート
Estimated: at 20 MHz with all three SCCs and IDMA active, the MC68302EH20C dissipates roughly 0.6-0.9 W. Provide at least one solid VCC/GND pair (pin 41/42, 120/121, 132/42) with low-impedance decoupling within 5 mm of each pair. Use 0.1 uF ceramic in parallel with 10 uF tantalum bulk; a 5 V linear regulator with adequate heatsinking is recommended over a switching regulator to keep ripple on the logic supply below 50 mVpp.
Because the MC68302EH20C is EOL, do not design a new production board around this part without a written last-time-buy commitment from NXP or a bonded-stock distributor. Stock and price fluctuate week-to-week, and counterfeit risk rises sharply for any lots arriving outside authorized channels. Use only franchised distributors or vetted independent brokers with documented traceability.
The 132-pin PQFP at 20 MHz places the design in moderate-speed territory; route the address and data buses as matched-length parallel groups with a 50 ohm controlled impedance and keep traces shorter than 75 mm where possible. Series-terminate the bus with 33 ohm resistors near the MPU for heavily loaded nets. Provide a clean RESET/HALT debounce circuit and verify clock-in duty cycle stays within 40-60%.
コンプライアンス情報
Original PQFP variants from the 1990s predate RoHS - the EH20C and earlier C/EH grades are typically NOT RoHS compliant. Only later 'AG' 3.3 V variants carried RoHS marking. RoHS/REACH/AEC-Q100 status to be confirmed against the specific lot marking before qualification.
