MC68302EH20C - 20MHz M683xx 8/16-Bit MPU | NXP | 132-PQFP
Référence : MC68302EH20C ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $32.4 | $324,00 |
| 100 | $26.75 | $2 675,00 |
| 500 | $22.1 | $11 050,00 |
| 1 000 | $19.85 | $19 850,00 |
MC68302EH20C Présentation
What is an M683xx microprocessor? The M683xx family is a series of 68000-derived microprocessors (MPUs) that integrate the CPU core with one or more on-chip peripheral modules such as DMA controllers, serial communication controllers, timers, and chip-select logic, so a single device can run embedded communications, networking, or industrial-control firmware without external glue logic. Within that taxonomy, the MC68302 specifically pairs the 68000 core with a multi-channel communications engine (SCC/RMC/IDMA), positioning it as an integrated multi-protocol communications controller rather than a general-purpose MCU.
Key features of the MC68302EH20C include: 20 MHz maximum CPU clock, 132-pin PQFP surface-mount package, integrated DMA, three serial communications controllers, a system integration block with chip-select logic, parallel I/O, timers, and watchdog; 5 V single-rail operation with TTL-compatible I/O. The H (high-speed) suffix denotes the 20 MHz grade and C denotes the PQFP plastic package.
Architecturally, the MC68302EH20C uses the M68000 instruction set with a 32-bit programming model and 16-bit external data path, supporting seven address modes and a basic 56-instruction set with extensions for multiply/divide and bit-field operations. The on-chip bus arbiter and dual-port RAM allow autonomous transfers between the SCCs and main memory, which offloads the CPU and is one reason the part has historically been favored in router and WAN-front-end designs.
Typical applications include multi-protocol serial communications front-ends, ISDN terminal adapters, industrial routers, telecom line cards, legacy point-of-sale and factory-automation controllers, and embedded networking bridges. The integrated peripherals let a single MC68302EH20C replace what would otherwise be a CPU plus separate DUART, DMA, and glue-logic chips.
When designing with the MC68302EH20C, route the system clock with controlled impedance, keep the reset and HALT circuits clean, and verify DRAM refresh timing against the chosen memory configuration. Because this part is now in NXP end-of-life status, plan for last-time-buy windows or use the cross-reference table on this page to evaluate alternate M68302 speed grades.
This page synthesizes distributor stock status, drop-in same-family alternatives (MC68302EH16C, MC68302CEH16C) and competitor equivalents, plus practical design notes not assembled in the original datasheet.
Alternatives de remplacement direct pour MC68302EH20C — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec MC68302EH20C (même facteur de forme et même empreinte) — différant par Data Bus Width, Package, Instruction Set, Maximum Clock Frequency, Mounting Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
MC68302EH16C
✅ Remplacement direct✓ En stock
$17.1 / unité
Voir la fiche technique →MC68302CEH16C
✅ Remplacement direct✓ En stock
$49.9 / unité
Voir la fiche technique →MC68302EH20B
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
MC68302EH20C Valeurs maximales et caractéristiques électriques
| Family | M68000 / M683xx |
| Core | M68000 (8/16-bit external data bus) |
| Number of Cores | 1 |
| Largeur du bus de données | 8/16-bit |
| Address Bus Width | 24-bit |
| Fréquence d'horloge maximale | 20 MHz |
| Speed Grade Suffix | EH20 (20 MHz, high-speed) |
| Package Suffix | C (PQFP plastic) |
| Boîtier | 132-PQFP (24.13 x 24.13 mm) |
| Nombre de broches | 132 |
| Type de montage | Surface Mount |
| Tension d'alimentation | 5 V nominal |
| On-chip Peripherals | 3 SCC, IDMA, Chip-Select, Timers, Watchdog, Parallel I/O |
| Instruction Set | M68000 (56 base instructions + extensions) |
Configuration des broches de MC68302EH20C
| Broche 1 | A23 — Address bus bit 23 |
| Broche 2 | A22 — Address bus bit 22 |
| Broche 3 | A21 — Address bus bit 21 |
| Broche 4 | A20 — Address bus bit 20 |
| Broche 5 | A19 — Address bus bit 19 |
| Broche 6 | A18 — Address bus bit 18 |
| Broche 7 | A17 — Address bus bit 17 |
| Broche 8 | A16 — Address bus bit 16 |
| Broche 9 | A15 — Address bus bit 15 |
| Broche 10 | A14 — Address bus bit 14 |
| Broche 11 | A13 — Address bus bit 13 |
| Broche 12 | A12 — Address bus bit 12 |
| Broche 13 | A11 — Address bus bit 11 |
| Broche 14 | A10 — Address bus bit 10 |
| Broche 15 | A9 — Address bus bit 9 |
| Broche 16 | A8 — Address bus bit 8 |
| Broche 17 | A7 — Address bus bit 7 |
| Broche 18 | A6 — Address bus bit 6 |
| Broche 19 | A5 — Address bus bit 5 |
| Broche 20 | A4 — Address bus bit 4 |
| Broche 21 | A3 — Address bus bit 3 |
| Broche 22 | A2 — Address bus bit 2 |
| Broche 23 | A1 — Address bus bit 1 |
| Broche 24 | A0 — Address bus bit 0 |
| Broche 25 | D15 — Data bus bit 15 |
| Broche 26 | D14 — Data bus bit 14 |
| Broche 27 | D13 — Data bus bit 13 |
| Broche 28 | D12 — Data bus bit 12 |
| Broche 29 | D11 — Data bus bit 11 |
| Broche 30 | D10 — Data bus bit 10 |
| Broche 31 | D9 — Data bus bit 9 |
| Broche 32 | D8 — Data bus bit 8 |
| Broche 33 | D7 — Data bus bit 7 |
| Broche 34 | D6 — Data bus bit 6 |
| Broche 35 | D5 — Data bus bit 5 |
| Broche 36 | D4 — Data bus bit 4 |
| Broche 37 | D3 — Data bus bit 3 |
| Broche 38 | D2 — Data bus bit 2 |
| Broche 39 | D1 — Data bus bit 1 |
| Broche 40 | D0 — Data bus bit 0 |
| Broche 41 | VCC — +5V supply |
| Broche 42 | GND — Ground |
| Broche 43 | CLKIN — System clock input |
| Broche 44 | RESET — Reset input (active low) |
| Broche 45 | HALT — Halt input (active low) |
| Broche 46 | AS — Address Strobe |
| Broche 47 | DS — Data Strobe |
| Broche 48 | R/W — Read/Write control |
| Broche 49 | BR — Bus Request |
| Broche 50 | BG — Bus Grant |
| Broche 51 | BGACK — Bus Grant Acknowledge |
| Broche 52 | IPL0 — Interrupt Priority Level 0 |
| Broche 53 | IPL1 — Interrupt Priority Level 1 |
| Broche 54 | IPL2 — Interrupt Priority Level 2 |
| Broche 55 | FC0 — Function Code 0 |
| Broche 56 | FC1 — Function Code 1 |
| Broche 57 | FC2 — Function Code 2 |
| Broche 58 | CS0 — Chip Select 0 |
| Broche 59 | CS1 — Chip Select 1 |
| Broche 60 | CS2 — Chip Select 2 |
| Broche 61 | CS3 — Chip Select 3 |
| Broche 62 | CS4 — Chip Select 4 |
| Broche 63 | CS5 — Chip Select 5 |
| Broche 64 | CS6 — Chip Select 6 |
| Broche 65 | CS7 — Chip Select 7 |
| Broche 66 | PA0 — Parallel I/O Port A bit 0 |
| Broche 67 | PA1 — Parallel I/O Port A bit 1 |
| Broche 68 | PA2 — Parallel I/O Port A bit 2 |
| Broche 69 | PA3 — Parallel I/O Port A bit 3 |
| Broche 70 | PA4 — Parallel I/O Port A bit 4 |
| Broche 71 | PA5 — Parallel I/O Port A bit 5 |
| Broche 72 | PA6 — Parallel I/O Port A bit 6 |
| Broche 73 | PA7 — Parallel I/O Port A bit 7 |
| Broche 74 | PA8 — Parallel I/O Port A bit 8 |
| Broche 75 | PA9 — Parallel I/O Port A bit 9 |
| Broche 76 | PA10 — Parallel I/O Port A bit 10 |
| Broche 77 | PA11 — Parallel I/O Port A bit 11 |
| Broche 78 | PA12 — Parallel I/O Port A bit 12 |
| Broche 79 | PA13 — Parallel I/O Port A bit 13 |
| Broche 80 | PA14 — Parallel I/O Port A bit 14 |
| Broche 81 | PA15 — Parallel I/O Port A bit 15 |
| Broche 82 | PB0 — Parallel I/O Port B bit 0 |
| Broche 83 | PB1 — Parallel I/O Port B bit 1 |
| Broche 84 | PB2 — Parallel I/O Port B bit 2 |
| Broche 85 | PB3 — Parallel I/O Port B bit 3 |
| Broche 86 | PB4 — Parallel I/O Port B bit 4 |
| Broche 87 | PB5 — Parallel I/O Port B bit 5 |
| Broche 88 | PB6 — Parallel I/O Port B bit 6 |
| Broche 89 | PB7 — Parallel I/O Port B bit 7 |
| Broche 90 | PB8 — Parallel I/O Port B bit 8 |
| Broche 91 | PB9 — Parallel I/O Port B bit 9 |
| Broche 92 | PB10 — Parallel I/O Port B bit 10 |
| Broche 93 | PB11 — Parallel I/O Port B bit 11 |
| Broche 94 | PB12 — Parallel I/O Port B bit 12 |
| Broche 95 | PB13 — Parallel I/O Port B bit 13 |
| Broche 96 | PB14 — Parallel I/O Port B bit 14 |
| Broche 97 | PB15 — Parallel I/O Port B bit 15 |
| Broche 98 | TXD1 — SCC1 Transmit Data |
| Broche 99 | RXD1 — SCC1 Receive Data |
| Broche 100 | RTS1 — SCC1 Request To Send |
| Broche 101 | CTS1 — SCC1 Clear To Send |
| Broche 102 | CD1 — SCC1 Carrier Detect |
| Broche 103 | TXD2 — SCC2 Transmit Data |
| Broche 104 | RXD2 — SCC2 Receive Data |
| Broche 105 | RTS2 — SCC2 Request To Send |
| Broche 106 | CTS2 — SCC2 Clear To Send |
| Broche 107 | CD2 — SCC2 Carrier Detect |
| Broche 108 | TXD3 — SCC3 Transmit Data |
| Broche 109 | RXD3 — SCC3 Receive Data |
| Broche 110 | RTS3 — SCC3 Request To Send |
| Broche 111 | CTS3 — SCC3 Clear To Send |
| Broche 112 | CD3 — SCC3 Carrier Detect |
| Broche 113 | TIN1 — Timer 1 Input |
| Broche 114 | TOUT1 — Timer 1 Output |
| Broche 115 | TIN2 — Timer 2 Input |
| Broche 116 | TOUT2 — Timer 2 Output |
| Broche 117 | DREQ — IDMA Request |
| Broche 118 | DACK — IDMA Acknowledge |
| Broche 119 | DONE — IDMA Done |
| Broche 120 | VCC — +5V supply |
| Broche 121 | GND — Ground |
| Broche 122 | AVEC — Autovector |
| Broche 123 | DSACK0 — Data Transfer and Size Acknowledge 0 |
| Broche 124 | DSACK1 — Data Transfer and Size Acknowledge 1 |
| Broche 125 | BERR — Bus Error |
| Broche 126 | BR0 — Bus Request 0 |
| Broche 127 | BR1 — Bus Request 1 |
| Broche 128 | TA — Transfer Acknowledge |
| Broche 129 | TBI — Transfer Burst Inhibit |
| Broche 130 | RMC — Read-Modify-Write Cycle |
| Broche 131 | MMUDIS — MMU Disable |
| Broche 132 | VCC — +5V supply |
Applications typiques
MC68302EH20C convient pour 6 applications: Multi-Protocol Serial Communications Front-End, Industrial Router and Bridge Controller, ISDN Terminal Adapter, Telecom Line Card and Channel Bank, Legacy Point-of-Sale Terminal, Factory-Automation Controller (Legacy).
Multi-Protocol Serial Communications Front-End
The MC68302EH20C's three on-chip Serial Communications Controllers (SCCs) and Independent DMA controller (IDMA) make it a natural fit for multi-protocol serial front-ends. Each SCC supports HDLC/SDLC, async, BISYNC, and transparent protocols, so a single 20 MHz device replaces a CPU plus three external DUARTs. In WAN-edge and serial-bridge designs the part offloads framing and DMA, leaving the M68000 core free to run routing or control firmware with no router restarts.
Recommandé
Industrial Router and Bridge Controller
Integrated chip-select logic, dual timers, parallel I/O and three SCCs let the MC68302EH20C serve as a one-chip industrial router or field-bridge controller. The on-chip peripheral integration reduces board area and BOM count versus a CPU-plus-glue design. At 20 MHz and 5 V the part delivers deterministic interrupt latency suitable for serial-field bridging on factory floors, and the watchdog timer protects unattended installations from firmware hangs.
Recommandé
ISDN Terminal Adapter
The MC68302EH20C was specifically designed for ISDN terminal-adapter and basic-rate-access designs, leveraging its three SCCs to terminate the ISDN BRI 'S' interface, drive an external codec, and maintain the D-channel signaling stack. The 20 MHz EH20C speed grade provides the throughput needed for ISDN call control plus echo-cancellation firmware, while the 5 V tolerant bus interfaces cleanly to legacy analog line interfaces.
Recommandé
Telecom Line Card and Channel Bank
Central-office line cards and channel banks historically deployed the MC68302EH20C because each SCC terminates a T1/E1 timeslot and the IDMA streams PCM samples to and from a serial backplane without CPU intervention. The 132-pin PQFP provides enough I/O for backplane glue and per-channel control, and the chip-select block can directly drive framers and codecs without external logic.
Recommandé
Legacy Point-of-Sale Terminal
POS terminals that need multiple serial ports for barcode scanners, receipt printers, and PIN pads historically use the MC68302EH20C because the three on-chip SCCs and parallel I/O handle all peripherals in a single chip. The integrated chip-select logic also drives character LCDs and keypads directly. While the part is EOL, deployed fleets continue to use it for service and repair with distributor-bonded stock.
Recommandé
Factory-Automation Controller (Legacy)
Discrete I/O, timers, and three SCCs make the MC68302EH20C a viable single-chip PLC-like controller for legacy factory-automation cells running RS-485 multi-drop fieldbuses. The 5 V supply and 132-pin PQFP remain compatible with 1990s-era backplanes, easing field-sustainment. The watchdog and chip-select block enable deterministic safety behaviors required by industrial standards of the era.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour MC68302EH20C — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | MC68302EH16C | MC68302CEH16C | MC68302EH20B |
|---|---|---|---|---|
| Package | 132-PQFP (24.13x24.13) | 132-PQFP (24.13x24.13) - same | 132-PQFP (24.13x24.13) - same | 132-PQFP (24.13x24.13) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Maximum Clock Frequency | 20 MHz | 16 MHz (-20%) | 16 MHz (-20%) | 20 MHz (same) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) |
| Data Bus Width | 8/16-bit | 8/16-bit (same) | 8/16-bit (same) | 8/16-bit (same) |
| On-chip SCCs | 3 | 3 (same) | 3 (same) | 3 (same) |
| IDMA Channels | 1 | 1 (same) | 1 (same) | 1 (same) |
| Lifecycle Status | EOL | EOL | EOL | EOL |
Principaux différenciateurs
- 20 MHz speed grade within M68302 family (vs MC68302EH16C)
- Integrated communications engine (3 SCCs + IDMA) (vs MC68040RC40A)
- 5 V supply tolerant I/O (vs MC68302AG16VC)
Notes de conception
Estimated: at 20 MHz with all three SCCs and IDMA active, the MC68302EH20C dissipates roughly 0.6-0.9 W. Provide at least one solid VCC/GND pair (pin 41/42, 120/121, 132/42) with low-impedance decoupling within 5 mm of each pair. Use 0.1 uF ceramic in parallel with 10 uF tantalum bulk; a 5 V linear regulator with adequate heatsinking is recommended over a switching regulator to keep ripple on the logic supply below 50 mVpp.
Because the MC68302EH20C is EOL, do not design a new production board around this part without a written last-time-buy commitment from NXP or a bonded-stock distributor. Stock and price fluctuate week-to-week, and counterfeit risk rises sharply for any lots arriving outside authorized channels. Use only franchised distributors or vetted independent brokers with documented traceability.
The 132-pin PQFP at 20 MHz places the design in moderate-speed territory; route the address and data buses as matched-length parallel groups with a 50 ohm controlled impedance and keep traces shorter than 75 mm where possible. Series-terminate the bus with 33 ohm resistors near the MPU for heavily loaded nets. Provide a clean RESET/HALT debounce circuit and verify clock-in duty cycle stays within 40-60%.
Informations de conformité
Original PQFP variants from the 1990s predate RoHS - the EH20C and earlier C/EH grades are typically NOT RoHS compliant. Only later 'AG' 3.3 V variants carried RoHS marking. RoHS/REACH/AEC-Q100 status to be confirmed against the specific lot marking before qualification.
