TPS566231 - 6A 18V Sync D-CAP3 Buck Regulator | TI
N.º de pieza: TPS566231 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $1.85 | $1,85 |
| 10 | $1.66 | $16,60 |
| 100 | $1.35 | $135,00 |
| 500 | $1.12 | $560,00 |
| 1.000 | $0.95 | $950,00 |
TPS566231 Descripción general
A synchronous buck converter is a type of DC-DC step-down regulator that uses two integrated transistors (high-side and low-side MOSFETs) to efficiently convert a higher input voltage to a lower output voltage. Unlike asynchronous converters that use a diode for the low-side, synchronous converters replace it with a low-resistance MOSFET, reducing conduction losses and improving efficiency, especially at high output currents. The TPS566231 belongs to the broader family of switching voltage regulators, essential power management ICs that convert and stabilize supply rails in electronic systems.
Key features include ultra-low quiescent current (ULQ) for low-bias operation, adjustable soft-start via the SS pin, and up to 98% duty cycle support for low dropout between input and output. Protection is comprehensive: overvoltage protection (OVP), overcurrent protection (OCP), undervoltage lockout (UVLO), overtemperature protection (OTP), and undervoltage protection (UVP) with hiccup mode. The PG (power good) pin is available on the TPS566231P variant for power sequencing in multi-rail systems.
The device uses TI's D-CAP3 control architecture, which provides fast transient response without external compensation, simplifying design. Integrated FETs and the compact 9-pin PowerVFQFN package minimize board space, while datasheet efficiency curves show peak efficiency above 90% for typical 12V-to-5V conversions.
Typical applications include point-of-load (POL) converters in networking equipment, servers, storage systems, and industrial automation, powering FPGAs, ASICs, and processors where 6A capability and a wide 3V-to-18V input range matter. Pulse skip mode maintains high efficiency at light loads.
When designing, select input and output capacitors carefully for stability and low ripple, and use the SS pin to control inrush current during startup.
Alternativas directas para TPS566231 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
TPS566238RQFR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
TPS566231PRQFR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
TPS566238PRQFR
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
TPS566231 Valores máximos y características eléctricas
| Topología | Synchronous Step-Down (Buck) |
| Rango de tensión de entrada | 3 V to 18 V |
| Corriente de salida máxima | 6 A |
| Tensión de salida | Adjustable, 0.6 V reference |
| Número de salidas | 1 |
| Control Architecture | D-CAP3 |
| Light Load Mode | Pulse Skip Mode |
| Maximum Duty Cycle | 98% |
| Arranque suave | Adjustable via SS pin |
| Power Good Indicator | No (PG on TPS566231P variant) |
| Protection Features | OVP, OCP, UVLO, OTP, UVP with hiccup |
| Encapsulado | 9-PowerVFQFN (RQF) |
| Tipo de montaje | Surface Mount |
| FETs | Integrated high-side and low-side MOSFETs |
Configuración de pines de TPS566231
| Pin 1 | EN — Enable input, logic level |
| Pin 2 | SS — Soft-start programming pin |
| Pin 3 | VIN — Input supply, 3V to 18V |
| Pin 4 | SW — Switch node, connect to inductor |
| Pin 5 | PGND — Power ground |
| Pin 6 | VBST — Bootstrap for high-side gate driver |
| Pin 7 | FB — Feedback input, 0.6V reference |
| Pin 8 | AGND — Analog ground |
| Pin 9 | VREG5 — Internal 5V LDO output / decoupling |
Aplicaciones típicas
TPS566231 es adecuado para 6 aplicacións: Networking Equipment POL Power, Server and Storage Power, Industrial Automation, FPGA and ASIC Power, Battery-Powered and Low-Bias Systems, Evaluation and Reference Design.
Networking Equipment POL Power
The TPS566231 fits switch, router, and access-point point-of-load rails where a 12V intermediate bus must step down to 5V or lower at up to 6A. Its 3V-to-18V input tolerates 12V bus variation, and D-CAP3 control delivers fast transient response to sudden traffic-driven load steps without external compensation. Pulse skip mode keeps light-load efficiency high for standby ports. Peak efficiency exceeds 90% in typical 12V-to-5V conversions per TI datasheet curves, minimizing thermal load in sealed enclosures.
Recomendado
Server and Storage Power
In servers and SSD/NAS storage, the TPS566231 powers auxiliary and peripheral rails from 12V backplanes. Full protection (OVP, OCP, UVLO, OTP, UVP-hiccup) suits environments with hot-plug faults, while the 9-pin PowerVFQFN saves board space near drive bays. Use the TPS566231P variant where a PG signal sequences rails for processors or ASICs. Adjustable SS soft-start limits inrush when multiple converters start from a shared bulk capacitor bank.
Recomendado
Industrial Automation
Factory systems commonly distribute 24V that is pre-regulated to 12V; the TPS566231 then efficiently creates 5V, 3.3V, or lower rails for sensors, controllers, and communication modules. Its wide 3V-to-18V input absorbs bus sag, the hiccup-mode UVP survives persistent short circuits on actuator harnesses, and OTP protects against enclosure overheating. ULQ ultra-low quiescent current benefits always-on monitoring nodes powered through limited bias supplies.
Recomendado
FPGA and ASIC Power
FPGA and ASIC I/O and auxiliary banks often need 5A-to-6A at 1.0V-to-2.5V from a 12V rail. The TPS566231 adjustable output (0.6V reference) covers these levels, and D-CAP3 fast transient response handles the sharp load transients typical of switching logic fabric. Pairing with the TPS566231P variant provides PG flagging so upsteam supervisors can sequence core rails before I/O, protecting multi-rail devices.
Recomendado
Battery-Powered and Low-Bias Systems
With 3V minimum input, the TPS566231 accepts 4S lithium-ion packs (12V-16.8V) or regulated battery buses, and ULQ ultra-low quiescent current minimizes standby drain. Pulse skip mode preserves efficiency at light standby loads common in battery-backed industrial devices and portable test instruments. The adjustable SS pin limits inrush from battery protection circuitry at power-up, and integrated FETs remove the cost and area of external power stages.
Recomendado
Evaluation and Reference Design
TI offers the TPS566231EVM evaluation board (a D-CAP3 non-isolated step-down design) to accelerate prototypes. Engineers can validate efficiency, transient response, and loop behavior against datasheet curves before committing a layout. The EVM demonstrates recommended inductor, capacitor, and feedback component values for 12V-input operation, providing a proven starting point for 6A POL rails in networking, server, and industrial products.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para TPS566231 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | TPS566238RQFR | TPS566231PRQFR | TPS566238PRQFR |
|---|---|---|---|---|
| Package | 9-PowerVFQFN (RQF) | 9-PowerVFQFN (RQF) - same | 9-PowerVFQFN (RQF) - same | 9-PowerVFQFN (RQF) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Input Voltage Range | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V |
| Output Current | 6 A | 6 A | 6 A | 6 A |
| Control Topology | D-CAP3, pulse skip | D-CAP3, pulse skip | D-CAP3, pulse skip | D-CAP3, pulse skip |
| Power Good (PG) Pin | No | No | Yes | Yes |
| Soft Start | Adjustable via SS pin | Adjustable via SS pin | Adjustable via SS pin | Adjustable via SS pin |
| Protection | OVP, OCP, UVLO, OTP, UVP hiccup | OVP, OCP, UVLO, OTP, UVP hiccup | OVP, OCP, UVLO, OTP, UVP hiccup | OVP, OCP, UVLO, OTP, UVP hiccup |
Diferenciadores clave
- ULQ ultra-low quiescent current with pulse skip (frente a TPS566238RQFR)
- 98% maximum duty cycle (frente a TPS54302QDDCRQ1 (4A class))
- D-CAP3 control with no external compensation (frente a TPS53624 (controller + external FETs))
Notas de diseño
Keep the SW node, input capacitor loop, and bootstrap capacitor loop as small as possible: place the input ceramic capacitor(s) within 2-3 mm of VIN and PGND, and the bootstrap cap directly across VBST and SW. Use solid PGND pour on layers 2-3 tied to the PowerVFQFN thermal pad with multiple vias; the integrated 6A FETs dump all switching losses into this pad, so copper area directly sets junction temperature.
For 12V-to-5V at 6A, verify inductor saturation rating above the OCP current threshold and choose output capacitance for the load transient targets; D-CAP3 uses the output ripple for regulation, so avoid excessive low-ESR-only capacitance stacking that starves the FB ripple. A mix of a small ESR capacitor and ceramics (per EVM BOM in TI datasheet SLUSB document set) preserves stability and fast transient response.
Do not exceed 18V input including transients - bulk bus ringing above VIN abs max destroys the integrated FETs. Reserve the base TPS566231 for single-rail designs; if multi-rail sequencing or supervisor handshaking is required, select TPS566231P (PG pin) before layout since the function is die-configured, not added externally. Set SS capacitor per inrush limits of upstream bulk caps.
Información de cumplimiento
RoHS and lead-free per TI product page ordering data. Verify AEC-Q100 status on TI.com quality pages - not indicated in provided data.
